Merge ktlim@zizzer:/bk/m5

into  zamp.eecs.umich.edu:/z/ktlim2/m5-shadowregs

arch/alpha/ev5.cc:
    Remove intr_post, it is no longer used.
arch/alpha/isa_traits.hh:
    Hand merge.

--HG--
extra : convert_revision : 94f14539a9e5646f8c368b15b2dff18ab2f492cf

11 files changed, 183 insertions, 135 deletions

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index c6da628be..e313c1a1c 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -46,35 +46,12 @@ using namespace EV5;
 
 ////////////////////////////////////////////////////////////////////////
 //
-//
-//
-void
-AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
-{
-    if (regs->pal_shadow == use_shadow)
-        panic("swap_palshadow: wrong PAL shadow state");
-
-    regs->pal_shadow = use_shadow;
-
-    for (int i = 0; i < NumIntRegs; i++) {
-        if (reg_redir[i]) {
-            IntReg temp = regs->intRegFile[i];
-            regs->intRegFile[i] = regs->palregs[i];
-            regs->palregs[i] = temp;
-        }
-    }
-}
-
-////////////////////////////////////////////////////////////////////////
-//
 //  Machine dependent functions
 //
 void
 AlphaISA::initCPU(RegFile *regs, int cpuId)
 {
     initIPRs(&regs->miscRegs, cpuId);
-    // CPU comes up with PAL regs enabled
-    swap_palshadow(regs, true);
 
     regs->intRegFile[16] = cpuId;
     regs->intRegFile[0] = cpuId;
@@ -83,12 +60,6 @@ AlphaISA::initCPU(RegFile *regs, int cpuId)
     regs->npc = regs->pc + sizeof(MachInst);
 }
 
-const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
-    /*  0 */ 0, 0, 0, 0, 0, 0, 0, 0,
-    /*  8 */ 1, 1, 1, 1, 1, 1, 1, 0,
-    /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
-    /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
-
 ////////////////////////////////////////////////////////////////////////
 //
 //
@@ -163,33 +134,6 @@ AlphaISA::zeroRegisters(CPU *cpu)
     cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
 }
 
-void
-AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
-{
-/*    bool use_pc = (fault == NoFault);
-
-    if (fault->isA<ArithmeticFault>())
-        panic("arithmetic faults NYI...");
-
-    // compute exception restart address
-    if (use_pc || fault->isA<PalFault>() || fault->isA<ArithmeticFault>()) {
-        // traps...  skip faulting instruction
-        regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc + 4);
-    } else {
-        // fault, post fault at excepting instruction
-        regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc);
-    }
-
-    // jump to expection address (PAL PC bit set here as well...)
-    if (!use_pc)
-        regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) +
-            (dynamic_cast<AlphaFault *>(fault.get()))->vect();
-    else
-        regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + pc;
-*/
-    // that's it! (orders of magnitude less painful than x86)
-}
-
 Fault
 ExecContext::hwrei()
 {
@@ -201,9 +145,6 @@ ExecContext::hwrei()
     if (!misspeculating()) {
         kernelStats->hwrei();
 
-        if ((readMiscReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0)
-            AlphaISA::swap_palshadow(&regs, false);
-
         cpu->checkInterrupts = true;
     }
 
diff --git a/arch/alpha/isa/branch.isa b/arch/alpha/isa/branch.isa
index 9a7fb9d79..b528df938 100644
--- a/arch/alpha/isa/branch.isa
+++ b/arch/alpha/isa/branch.isa
@@ -46,7 +46,7 @@ output header {{
         mutable const SymbolTable *cachedSymtab;
 
         /// Constructor
-        PCDependentDisassembly(const char *mnem, MachInst _machInst,
+        PCDependentDisassembly(const char *mnem, ExtMachInst _machInst,
                                OpClass __opClass)
             : AlphaStaticInst(mnem, _machInst, __opClass),
               cachedPC(0), cachedSymtab(0)
@@ -68,7 +68,7 @@ output header {{
         int32_t disp;
 
         /// Constructor.
-        Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
+        Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
             : PCDependentDisassembly(mnem, _machInst, __opClass),
               disp(BRDISP << 2)
         {
@@ -93,7 +93,7 @@ output header {{
 
       public:
         /// Constructor
-        Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
+        Jump(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
             : PCDependentDisassembly(mnem, _machInst, __opClass),
               disp(BRDISP)
         {
diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa
index 2fb3fbd2a..54bc97920 100644
--- a/arch/alpha/isa/decoder.isa
+++ b/arch/alpha/isa/decoder.isa
@@ -681,7 +681,6 @@ decode OPCODE default Unknown::unknown() {
             bool dopal = xc->simPalCheck(palFunc);
 
             if (dopal) {
-                AlphaISA::swap_palshadow(&xc->xcBase()->regs, true);
                 xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC);
                 NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
             }
@@ -705,50 +704,56 @@ decode OPCODE default Unknown::unknown() {
 #endif
 
 #if FULL_SYSTEM
-    format HwLoad {
-        0x1b: decode HW_LDST_QUAD {
-            0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
-            1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
+    0x1b: decode PALMODE {
+        0: OpcdecFault::hw_st_quad();
+        1: decode HW_LDST_QUAD {
+            format HwLoad {
+                0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
+                1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
+            }
         }
     }
 
-    format HwStore {
-        0x1f: decode HW_LDST_COND {
-            0: decode HW_LDST_QUAD {
-                0: hw_st({{ EA = (Rb + disp) & ~3; }},
-                         {{ Mem.ul = Ra<31:0>; }}, L);
-                1: hw_st({{ EA = (Rb + disp) & ~7; }},
-                         {{ Mem.uq = Ra.uq; }}, Q);
-            }
+    0x1f: decode PALMODE {
+        0: OpcdecFault::hw_st_cond();
+        format HwStore {
+            1: decode HW_LDST_COND {
+                0: decode HW_LDST_QUAD {
+                    0: hw_st({{ EA = (Rb + disp) & ~3; }},
+                {{ Mem.ul = Ra<31:0>; }}, L);
+                    1: hw_st({{ EA = (Rb + disp) & ~7; }},
+                {{ Mem.uq = Ra.uq; }}, Q);
+                }
 
-            1: FailUnimpl::hw_st_cond();
+                1: FailUnimpl::hw_st_cond();
+            }
         }
     }
 
-    format HwMoveIPR {
-        0x19: hw_mfpr({{
-            // this instruction is only valid in PAL mode
-            if (!xc->inPalMode()) {
-                fault = new UnimplementedOpcodeFault;
-            }
-            else {
+    0x19: decode PALMODE {
+        0: OpcdecFault::hw_mfpr();
+        format HwMoveIPR {
+            1: hw_mfpr({{
                 Ra = xc->readMiscRegWithEffect(ipr_index, fault);
-            }
-        }});
-        0x1d: hw_mtpr({{
-            // this instruction is only valid in PAL mode
-            if (!xc->inPalMode()) {
-                fault = new UnimplementedOpcodeFault;
-            }
-            else {
+            }});
+        }
+    }
+
+    0x1d: decode PALMODE {
+        0: OpcdecFault::hw_mtpr();
+        format HwMoveIPR {
+            1: hw_mtpr({{
                 xc->setMiscRegWithEffect(ipr_index, Ra);
                 if (traceData) { traceData->setData(Ra); }
-            }
-        }});
+            }});
+        }
     }
 
     format BasicOperate {
-        0x1e: hw_rei({{ xc->hwrei(); }}, IsSerializing);
+        0x1e: decode PALMODE {
+            0: OpcdecFault::hw_rei();
+            1:hw_rei({{ xc->hwrei(); }}, IsSerializing);
+        }
 
         // M5 special opcodes use the reserved 0x01 opcode space
         0x01: decode M5FUNC {
diff --git a/arch/alpha/isa/fp.isa b/arch/alpha/isa/fp.isa
index 13656359f..f34c13c42 100644
--- a/arch/alpha/isa/fp.isa
+++ b/arch/alpha/isa/fp.isa
@@ -106,7 +106,7 @@ output header {{
         mutable bool warnedOnTrapping;
 
         /// Constructor
-        AlphaFP(const char *mnem, MachInst _machInst, OpClass __opClass)
+        AlphaFP(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
             : AlphaStaticInst(mnem, _machInst, __opClass),
               roundingMode((enum RoundingMode)FP_ROUNDMODE),
               trappingMode((enum TrappingMode)FP_TRAPMODE),
diff --git a/arch/alpha/isa/int.isa b/arch/alpha/isa/int.isa
index 049437f8c..17ecc1a51 100644
--- a/arch/alpha/isa/int.isa
+++ b/arch/alpha/isa/int.isa
@@ -37,7 +37,7 @@ output header {{
         uint8_t imm;
 
         /// Constructor
-        IntegerImm(const char *mnem, MachInst _machInst, OpClass __opClass)
+        IntegerImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
             : AlphaStaticInst(mnem, _machInst, __opClass), imm(INTIMM)
         {
         }
diff --git a/arch/alpha/isa/main.isa b/arch/alpha/isa/main.isa
index ad9c2a55e..17c9989ab 100644
--- a/arch/alpha/isa/main.isa
+++ b/arch/alpha/isa/main.isa
@@ -79,6 +79,7 @@ namespace AlphaISA;
 //
 
 // Universal (format-independent) fields
+def bitfield PALMODE    <32:32>;
 def bitfield OPCODE	<31:26>;
 def bitfield RA		<25:21>;
 def bitfield RB		<20:16>;
@@ -153,9 +154,12 @@ def operands {{
     # Int regs default to unsigned, but code should not count on this.
     # For clarity, descriptions that depend on unsigned behavior should
     # explicitly specify '.uq'.
-    'Ra': ('IntReg', 'uq', 'RA', 'IsInteger', 1),
-    'Rb': ('IntReg', 'uq', 'RB', 'IsInteger', 2),
-    'Rc': ('IntReg', 'uq', 'RC', 'IsInteger', 3),
+    'Ra': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RA] : RA',
+           'IsInteger', 1),
+    'Rb': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RB] : RB',
+           'IsInteger', 2),
+    'Rc': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RC] : RC',
+           'IsInteger', 3),
     'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
     'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
     'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
@@ -200,7 +204,7 @@ output header {{
         };
 
         /// Constructor.
-        AlphaStaticInst(const char *mnem, MachInst _machInst,
+        AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
                         OpClass __opClass)
             : StaticInst(mnem, _machInst, __opClass)
         {
@@ -272,7 +276,7 @@ def template BasicDeclare {{
     {
       public:
         /// Constructor.
-        %(class_name)s(MachInst machInst);
+        %(class_name)s(ExtMachInst machInst);
 
         %(BasicExecDeclare)s
     };
@@ -280,7 +284,7 @@ def template BasicDeclare {{
 
 // Basic instruction class constructor template.
 def template BasicConstructor {{
-    inline %(class_name)s::%(class_name)s(MachInst machInst)
+    inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
          : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
     {
         %(constructor)s;
@@ -344,7 +348,7 @@ output header {{
 
       public:
         /// Constructor
-        Nop(const std::string _originalDisassembly, MachInst _machInst)
+        Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
             : AlphaStaticInst("nop", _machInst, No_OpClass),
               originalDisassembly(_originalDisassembly)
         {
@@ -428,6 +432,9 @@ def format BasicOperateWithNopCheck(code, *opt_args) {{
 // PAL instruction templates, formats, etc.
 ##include "m5/arch/alpha/isa/pal.isa"
 
+// Opcdec fault instruction templates, formats, etc.
+##include "m5/arch/alpha/isa/opcdec.isa"
+
 // Unimplemented instruction templates, formats, etc.
 ##include "m5/arch/alpha/isa/unimp.isa"
 
diff --git a/arch/alpha/isa/mem.isa b/arch/alpha/isa/mem.isa
index 61d6ea8fa..3c8b4f755 100644
--- a/arch/alpha/isa/mem.isa
+++ b/arch/alpha/isa/mem.isa
@@ -42,7 +42,7 @@ output header {{
         const StaticInstPtr memAccPtr;
 
         /// Constructor
-        Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
+        Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                StaticInstPtr _eaCompPtr = nullStaticInstPtr,
                StaticInstPtr _memAccPtr = nullStaticInstPtr)
             : AlphaStaticInst(mnem, _machInst, __opClass),
@@ -70,7 +70,7 @@ output header {{
         int32_t disp;
 
         /// Constructor.
-        MemoryDisp32(const char *mnem, MachInst _machInst, OpClass __opClass,
+        MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                      StaticInstPtr _eaCompPtr = nullStaticInstPtr,
                      StaticInstPtr _memAccPtr = nullStaticInstPtr)
             : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
@@ -89,7 +89,7 @@ output header {{
     {
       protected:
         /// Constructor
-        MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass,
+        MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                      StaticInstPtr _eaCompPtr = nullStaticInstPtr,
                      StaticInstPtr _memAccPtr = nullStaticInstPtr)
             : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
@@ -141,7 +141,7 @@ def template LoadStoreDeclare {{
         {
           public:
             /// Constructor
-            EAComp(MachInst machInst);
+            EAComp(ExtMachInst machInst);
 
             %(BasicExecDeclare)s
         };
@@ -153,7 +153,7 @@ def template LoadStoreDeclare {{
         {
           public:
             /// Constructor
-            MemAcc(MachInst machInst);
+            MemAcc(ExtMachInst machInst);
 
             %(BasicExecDeclare)s
         };
@@ -161,7 +161,7 @@ def template LoadStoreDeclare {{
       public:
 
         /// Constructor.
-        %(class_name)s(MachInst machInst);
+        %(class_name)s(ExtMachInst machInst);
 
         %(BasicExecDeclare)s
 
@@ -186,19 +186,19 @@ def template LoadStoreConstructor {{
     /** TODO: change op_class to AddrGenOp or something (requires
      * creating new member of OpClass enum in op_class.hh, updating
      * config files, etc.). */
-    inline %(class_name)s::EAComp::EAComp(MachInst machInst)
+    inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst)
         : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
     {
         %(ea_constructor)s;
     }
 
-    inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
+    inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst)
         : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
     {
         %(memacc_constructor)s;
     }
 
-    inline %(class_name)s::%(class_name)s(MachInst machInst)
+    inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
          : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                           new EAComp(machInst), new MemAcc(machInst))
     {
diff --git a/arch/alpha/isa/opcdec.isa b/arch/alpha/isa/opcdec.isa
new file mode 100644
index 000000000..bb2f91e5c
--- /dev/null
+++ b/arch/alpha/isa/opcdec.isa
@@ -0,0 +1,72 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+output header {{
+    /**
+     * Static instruction class for instructions that cause an OPCDEC fault
+     * when executed.  This is currently only for PAL mode instructions
+     * executed in non-PAL mode.
+     */
+    class OpcdecFault : public AlphaStaticInst
+    {
+      public:
+        /// Constructor
+        OpcdecFault(ExtMachInst _machInst)
+            : AlphaStaticInst("opcdec fault", _machInst, No_OpClass)
+        {
+        }
+
+        %(BasicExecDeclare)s
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+}};
+
+output decoder {{
+    std::string
+    OpcdecFault::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
+                        " OPCDEC fault", machInst, OPCODE);
+    }
+}};
+
+output exec {{
+    Fault
+    OpcdecFault::execute(%(CPU_exec_context)s *xc,
+                     Trace::InstRecord *traceData) const
+    {
+        return new UnimplementedOpcodeFault;
+    }
+}};
+
+def format OpcdecFault() {{
+    decode_block = 'return new OpcdecFault(machInst);\n'
+}};
+
diff --git a/arch/alpha/isa/pal.isa b/arch/alpha/isa/pal.isa
index 49e5bff12..e07bea5a8 100644
--- a/arch/alpha/isa/pal.isa
+++ b/arch/alpha/isa/pal.isa
@@ -36,7 +36,7 @@ output header {{
       protected:
 
         /// Constructor.
-        EmulatedCallPal(const char *mnem, MachInst _machInst,
+        EmulatedCallPal(const char *mnem, ExtMachInst _machInst,
                         OpClass __opClass)
             : AlphaStaticInst(mnem, _machInst, __opClass)
         {
@@ -83,7 +83,7 @@ output header {{
         bool palPriv;	///< is this call privileged?
 
         /// Constructor.
-        CallPalBase(const char *mnem, MachInst _machInst,
+        CallPalBase(const char *mnem, ExtMachInst _machInst,
                     OpClass __opClass);
 
         std::string
@@ -93,7 +93,7 @@ output header {{
 
 output decoder {{
     inline
-    CallPalBase::CallPalBase(const char *mnem, MachInst _machInst,
+    CallPalBase::CallPalBase(const char *mnem, ExtMachInst _machInst,
                              OpClass __opClass)
         : AlphaStaticInst(mnem, _machInst, __opClass),
         palFunc(PALFUNC)
@@ -148,7 +148,7 @@ output header {{
         int16_t disp;
 
         /// Constructor
-        HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass,
+        HwLoadStore(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                     StaticInstPtr _eaCompPtr = nullStaticInstPtr,
                     StaticInstPtr _memAccPtr = nullStaticInstPtr);
 
@@ -160,7 +160,7 @@ output header {{
 
 output decoder {{
     inline
-    HwLoadStore::HwLoadStore(const char *mnem, MachInst _machInst,
+    HwLoadStore::HwLoadStore(const char *mnem, ExtMachInst _machInst,
                              OpClass __opClass,
                              StaticInstPtr _eaCompPtr,
                              StaticInstPtr _memAccPtr)
@@ -231,7 +231,7 @@ output header {{
         int ipr_index;
 
         /// Constructor
-        HwMoveIPR(const char *mnem, MachInst _machInst, OpClass __opClass)
+        HwMoveIPR(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
             : AlphaStaticInst(mnem, _machInst, __opClass),
               ipr_index(HW_IPR_IDX)
         {
diff --git a/arch/alpha/isa/unimp.isa b/arch/alpha/isa/unimp.isa
index 09df39706..392522801 100644
--- a/arch/alpha/isa/unimp.isa
+++ b/arch/alpha/isa/unimp.isa
@@ -38,7 +38,7 @@ output header {{
     {
       public:
         /// Constructor
-        FailUnimplemented(const char *_mnemonic, MachInst _machInst)
+        FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
             : AlphaStaticInst(_mnemonic, _machInst, No_OpClass)
         {
             // don't call execute() (which panics) if we're on a
@@ -69,7 +69,7 @@ output header {{
 
       public:
         /// Constructor
-        WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
+        WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
             : AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
         {
             // don't call execute() (which panics) if we're on a
@@ -148,7 +148,7 @@ output header {{
     {
       public:
         /// Constructor
-        Unknown(MachInst _machInst)
+        Unknown(ExtMachInst _machInst)
             : AlphaStaticInst("unknown", _machInst, No_OpClass)
         {
             // don't call execute() (which panics) if we're on a
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index b8aeffdde..a551db485 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -57,15 +57,17 @@ namespace AlphaISA
 {
 
     typedef uint32_t MachInst;
+    typedef uint64_t ExtMachInst;
     typedef uint8_t  RegIndex;
 
     enum {
         MemoryEnd = 0xffffffffffffffffULL,
 
-        NumIntRegs = 32,
-        NumFloatRegs = 32,
+        NumIntArchRegs = 32,
+        NumPALShadowRegs = 8,
+        NumFloatArchRegs = 32,
         // @todo: Figure out what this number really should be.
-        NumMiscRegs = 32,
+        NumMiscArchRegs = 32,
 
         MaxRegsOfAnyType = 32,
         // Static instruction parameters
@@ -99,17 +101,23 @@ namespace AlphaISA
         DepNA = 0,
     };
 
+    enum {
+        NumIntRegs = NumIntArchRegs + NumPALShadowRegs,
+        NumFloatRegs = NumFloatArchRegs,
+        NumMiscRegs = NumMiscArchRegs
+    };
+
     // These enumerate all the registers for dependence tracking.
     enum DependenceTags {
         // 0..31 are the integer regs 0..31
         // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
-        FP_Base_DepTag = 32,
-        Ctrl_Base_DepTag = 64,
-        Fpcr_DepTag = 64,		// floating point control register
-        Uniq_DepTag = 65,
-        Lock_Flag_DepTag = 66,
-        Lock_Addr_DepTag = 67,
-        IPR_Base_DepTag = 68
+        FP_Base_DepTag = 40,
+        Ctrl_Base_DepTag = 72,
+        Fpcr_DepTag = 72,		// floating point control register
+        Uniq_DepTag = 73,
+        Lock_Flag_DepTag = 74,
+        Lock_Addr_DepTag = 75,
+        IPR_Base_DepTag = 76
     };
 
     typedef uint64_t IntReg;
@@ -131,6 +139,9 @@ extern const Addr PageBytes;
 extern const Addr PageMask;
 extern const Addr PageOffset;
 
+// redirected register map, really only used for the full system case.
+extern const int reg_redir[NumIntRegs];
+
 #if FULL_SYSTEM
 
     typedef uint64_t InternalProcReg;
@@ -198,9 +209,7 @@ extern const Addr PageOffset;
         Addr pc;			// program counter
         Addr npc;			// next-cycle program counter
 #if FULL_SYSTEM
-        IntReg palregs[NumIntRegs];	// PAL shadow registers
         int intrflag;			// interrupt flag
-        bool pal_shadow;		// using pal_shadow registers
         inline int instAsid()
         { return EV5::ITB_ASN_ASN(miscRegs.ipr[IPR_ITB_ASN]); }
         inline int dataAsid()
@@ -211,10 +220,12 @@ extern const Addr PageOffset;
         void unserialize(Checkpoint *cp, const std::string &section);
     };
 
-    StaticInstPtr decodeInst(MachInst);
+    static inline ExtMachInst makeExtMI(MachInst inst, const uint64_t &pc);
+
+    StaticInstPtr decodeInst(ExtMachInst);
 
     // return a no-op instruction... used for instruction fetch faults
-    extern const MachInst NoopMachInst;
+    extern const ExtMachInst NoopMachInst;
 
     enum annotes {
         ANNOTE_NONE = 0,
@@ -361,6 +372,18 @@ class SyscallReturn {
 
 #endif
 
+static inline AlphaISA::ExtMachInst
+AlphaISA::makeExtMI(AlphaISA::MachInst inst, const uint64_t &pc) {
+#if FULL_SYSTEM
+    AlphaISA::ExtMachInst ext_inst = inst;
+    if (pc && 0x1)
+        return ext_inst|=(static_cast<AlphaISA::ExtMachInst>(pc & 0x1) << 32);
+    else
+        return ext_inst;
+#else
+    return AlphaISA::ExtMachInst(inst);
+#endif
+}
 
 #if FULL_SYSTEM
 //typedef TheISA::InternalProcReg InternalProcReg;