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authorSteve Reinhardt <stever@eecs.umich.edu>2005-02-25 12:41:08 -0500
committerSteve Reinhardt <stever@eecs.umich.edu>2005-02-25 12:41:08 -0500
commit368882a847955c712c9248eaf0fe569228c8e0fb (patch)
treeac9baa598a93113e4cd8b00fd2f78119314474d9 /arch/alpha
parent107233adf166ef9a376358283073c697686e07c7 (diff)
downloadgem5-368882a847955c712c9248eaf0fe569228c8e0fb.tar.xz
Fix timing modeling of faults: functionally the very next instruction after
a faulting instruction is the fault handler, which appears as an independent instruction to the timing model. New code will stall fetch and not fetch the fault handler as long as there's a faulting instruction in the pipeline (i.e., the faulting inst has to commit first). Also fix Ali's bad-address assertion that doesn't apply to full system. Added some more debugging support in the process. Hopefully we'll move to the new cpu model soon and we won't need it anymore. arch/alpha/alpha_memory.cc: Reorganize lookup() so we can trace the result of the lookup as well. arch/alpha/isa_traits.hh: Add NoopMachInst (so we can insert them in the pipeline on ifetch faults). base/traceflags.py: Replace "Dispatch" flag with "Pipeline" (since I added similar DPRINTFs in other pipe stages). cpu/exetrace.cc: Change default for printing mis-speculated instructions to true (since that's often what we want, and right now you can't change it from the command line...). --HG-- extra : convert_revision : a29a98a373076d62bbbb1d6f40ba51ecae436dbc
Diffstat (limited to 'arch/alpha')
-rw-r--r--arch/alpha/alpha_memory.cc29
-rw-r--r--arch/alpha/isa_traits.hh3
2 files changed, 19 insertions, 13 deletions
diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index 639abbeb8..8f6d7a51a 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -68,24 +68,27 @@ AlphaTLB::~AlphaTLB()
AlphaISA::PTE *
AlphaTLB::lookup(Addr vpn, uint8_t asn) const
{
- DPRINTF(TLB, "lookup %#x, asn %#x\n", vpn, (int)asn);
+ // assume not found...
+ AlphaISA::PTE *retval = NULL;
PageTable::const_iterator i = lookupTable.find(vpn);
- if (i == lookupTable.end())
- return NULL;
-
- while (i->first == vpn) {
- int index = i->second;
- AlphaISA::PTE *pte = &table[index];
- assert(pte->valid);
- if (vpn == pte->tag && (pte->asma || pte->asn == asn))
- return pte;
+ if (i != lookupTable.end()) {
+ while (i->first == vpn) {
+ int index = i->second;
+ AlphaISA::PTE *pte = &table[index];
+ assert(pte->valid);
+ if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
+ retval = pte;
+ break;
+ }
- ++i;
+ ++i;
+ }
}
- // not found...
- return NULL;
+ DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
+ retval ? "hit" : "miss", retval ? retval->ppn : 0);
+ return retval;
}
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index ff3da1502..8db8c6994 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -175,6 +175,9 @@ static const Addr PageOffset = PageBytes - 1;
static StaticInstPtr<AlphaISA> decodeInst(MachInst);
+ // return a no-op instruction... used for instruction fetch faults
+ static const MachInst NoopMachInst;
+
enum annotes {
ANNOTE_NONE = 0,
// An impossible number for instruction annotations