Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed.

--HG--
extra : convert_revision : 5b2f457401f8ff94fe39fe071288eb117814b7bb

10 files changed, 73 insertions, 73 deletions

diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index 615ce92a4..d00186d95 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -303,7 +303,7 @@ AlphaITB::fault(Addr pc, ExecContext *xc) const
 }
 
 
-Fault *
+Fault
 AlphaITB::translate(MemReqPtr &req) const
 {
     InternalProcReg *ipr = req->xc->regs.ipr;
@@ -493,7 +493,7 @@ AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const
     }
 }
 
-Fault *
+Fault
 AlphaDTB::translate(MemReqPtr &req, bool write) const
 {
     RegFile *regs = &req->xc->regs;
@@ -575,7 +575,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
                 fault(req, (write ? MM_STAT_WR_MASK : 0) |
                       MM_STAT_DTB_MISS_MASK);
                 if (write) { write_misses++; } else { read_misses++; }
-                return (req->flags & VPTE) ? (Fault *)PDtbMissFault : (Fault *)NDtbMissFault;
+                return (req->flags & VPTE) ? (Fault)PDtbMissFault : (Fault)NDtbMissFault;
             }
 
             req->paddr = (pte->ppn << AlphaISA::PageShift) +
diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/alpha_memory.hh
index 849063f59..de955fa46 100644
--- a/arch/alpha/alpha_memory.hh
+++ b/arch/alpha/alpha_memory.hh
@@ -94,7 +94,7 @@ class AlphaITB : public AlphaTLB
     AlphaITB(const std::string &name, int size);
     virtual void regStats();
 
-    Fault * translate(MemReqPtr &req) const;
+    Fault translate(MemReqPtr &req) const;
 };
 
 class AlphaDTB : public AlphaTLB
@@ -120,7 +120,7 @@ class AlphaDTB : public AlphaTLB
     AlphaDTB(const std::string &name, int size);
     virtual void regStats();
 
-    Fault * translate(MemReqPtr &req, bool write) const;
+    Fault translate(MemReqPtr &req, bool write) const;
 };
 
 #endif // __ALPHA_MEMORY_HH__
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 72f48bfb2..4777907e0 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -85,7 +85,7 @@ AlphaISA::initCPU(RegFile *regs)
 // alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
 //
 const Addr
-AlphaISA::fault_addr(Fault * fault)
+AlphaISA::fault_addr(Fault fault)
 {
         //Check for the system wide faults
         if(fault == NoFault) return 0x0000;
@@ -177,7 +177,7 @@ AlphaISA::zeroRegisters(CPU *cpu)
 }
 
 void
-ExecContext::ev5_trap(Fault * fault)
+ExecContext::ev5_trap(Fault fault)
 {
     DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name, regs.pc);
     cpu->recordEvent(csprintf("Fault %s", fault->name));
@@ -209,7 +209,7 @@ ExecContext::ev5_trap(Fault * fault)
 
 
 void
-AlphaISA::intr_post(RegFile *regs, Fault * fault, Addr pc)
+AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
 {
     InternalProcReg *ipr = regs->ipr;
     bool use_pc = (fault == NoFault);
@@ -235,7 +235,7 @@ AlphaISA::intr_post(RegFile *regs, Fault * fault, Addr pc)
     // that's it! (orders of magnitude less painful than x86)
 }
 
-Fault *
+Fault
 ExecContext::hwrei()
 {
     uint64_t *ipr = regs.ipr;
@@ -259,7 +259,7 @@ ExecContext::hwrei()
 }
 
 uint64_t
-ExecContext::readIpr(int idx, Fault * &fault)
+ExecContext::readIpr(int idx, Fault &fault)
 {
     uint64_t *ipr = regs.ipr;
     uint64_t retval = 0;	// return value, default 0
@@ -370,7 +370,7 @@ ExecContext::readIpr(int idx, Fault * &fault)
 int break_ipl = -1;
 #endif
 
-Fault *
+Fault
 ExecContext::setIpr(int idx, uint64_t val)
 {
     uint64_t *ipr = regs.ipr;
diff --git a/arch/alpha/faults.cc b/arch/alpha/faults.cc
index e05b3fe59..fa4950198 100644
--- a/arch/alpha/faults.cc
+++ b/arch/alpha/faults.cc
@@ -57,24 +57,24 @@ PalFaultType * const PalFault =
 IntegerOverflowFaultType * const IntegerOverflowFault =
     new IntegerOverflowFaultType("intover", 16, 0x0501);
 
-Fault ** ListOfFaults[] = {
-        (Fault **)&NoFault,
-        (Fault **)&ResetFault,
-        (Fault **)&MachineCheckFault,
-        (Fault **)&ArithmeticFault,
-        (Fault **)&InterruptFault,
-        (Fault **)&NDtbMissFault,
-        (Fault **)&PDtbMissFault,
-        (Fault **)&AlignmentFault,
-        (Fault **)&DtbPageFault,
-        (Fault **)&DtbAcvFault,
-        (Fault **)&ItbMissFault,
-        (Fault **)&ItbPageFault,
-        (Fault **)&ItbAcvFault,
-        (Fault **)&UnimplementedOpcodeFault,
-        (Fault **)&FloatEnableFault,
-        (Fault **)&PalFault,
-        (Fault **)&IntegerOverflowFault,
+Fault * ListOfFaults[] = {
+        (Fault *)&NoFault,
+        (Fault *)&ResetFault,
+        (Fault *)&MachineCheckFault,
+        (Fault *)&ArithmeticFault,
+        (Fault *)&InterruptFault,
+        (Fault *)&NDtbMissFault,
+        (Fault *)&PDtbMissFault,
+        (Fault *)&AlignmentFault,
+        (Fault *)&DtbPageFault,
+        (Fault *)&DtbAcvFault,
+        (Fault *)&ItbMissFault,
+        (Fault *)&ItbPageFault,
+        (Fault *)&ItbAcvFault,
+        (Fault *)&UnimplementedOpcodeFault,
+        (Fault *)&FloatEnableFault,
+        (Fault *)&PalFault,
+        (Fault *)&IntegerOverflowFault,
         };
 
-int NumFaults = sizeof(ListOfFaults) / sizeof(Fault **);
+int NumFaults = sizeof(ListOfFaults) / sizeof(Fault *);
diff --git a/arch/alpha/faults.hh b/arch/alpha/faults.hh
index 60c9e735c..3e25adc4e 100644
--- a/arch/alpha/faults.hh
+++ b/arch/alpha/faults.hh
@@ -32,11 +32,11 @@
 #include "sim/faults.hh"
 #include "arch/isa_traits.hh" //For the Addr type
 
-class AlphaFault : public Fault
+class AlphaFault : public FaultBase
 {
   public:
     AlphaFault(char * newName, int newId, Addr newVect)
-        : Fault(newName, newId), vect(newVect)
+        : FaultBase(newName, newId), vect(newVect)
     {;}
 
     Addr vect;
@@ -154,7 +154,7 @@ extern class IntegerOverflowFaultType : public AlphaFault
     {;}
 } * const IntegerOverflowFault;
 
-extern Fault ** ListOfFaults[];
+extern Fault * ListOfFaults[];
 extern int NumFaults;
 
 #endif // __FAULTS_HH__
diff --git a/arch/alpha/isa/fp.isa b/arch/alpha/isa/fp.isa
index c718c5524..7e81fb830 100644
--- a/arch/alpha/isa/fp.isa
+++ b/arch/alpha/isa/fp.isa
@@ -32,16 +32,16 @@ output exec {{
     /// @retval Full-system mode: NoFault if FP is enabled, FenFault
     /// if not.  Non-full-system mode: always returns NoFault.
 #if FULL_SYSTEM
-    inline Fault * checkFpEnableFault(%(CPU_exec_context)s *xc)
+    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
-        Fault * fault = NoFault;	// dummy... this ipr access should not fault
+        Fault fault = NoFault;	// dummy... this ipr access should not fault
         if (!EV5::ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
             fault = FloatEnableFault;
         }
         return fault;
     }
 #else
-    inline Fault * checkFpEnableFault(%(CPU_exec_context)s *xc)
+    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
         return NoFault;
     }
@@ -199,7 +199,7 @@ output decoder {{
 // FP instruction class execute method template.  Handles non-standard
 // rounding modes.
 def template FloatingPointExecute {{
-    Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
         if (trappingMode != Imprecise && !warnedOnTrapping) {
@@ -208,7 +208,7 @@ def template FloatingPointExecute {{
             warnedOnTrapping = true;
         }
 
-        Fault * fault = NoFault;
+        Fault fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
@@ -242,7 +242,7 @@ def template FloatingPointExecute {{
 // rounding mode control is needed.  Like BasicExecute, but includes
 // check & warning for non-standard trapping mode.
 def template FPFixedRoundingExecute {{
-    Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
         if (trappingMode != Imprecise && !warnedOnTrapping) {
@@ -251,7 +251,7 @@ def template FPFixedRoundingExecute {{
             warnedOnTrapping = true;
         }
 
-        Fault * fault = NoFault;
+        Fault fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
diff --git a/arch/alpha/isa/main.isa b/arch/alpha/isa/main.isa
index 862b2b95e..b8d03c0be 100644
--- a/arch/alpha/isa/main.isa
+++ b/arch/alpha/isa/main.isa
@@ -258,7 +258,7 @@ output decoder {{
 
 // Declarations for execute() methods.
 def template BasicExecDeclare {{
-    Fault * execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+    Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
 }};
 
 // Basic instruction class declaration template.
@@ -287,10 +287,10 @@ def template BasicConstructor {{
 
 // Basic instruction class execute method template.
 def template BasicExecute {{
-    Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
-        Fault * fault = NoFault;
+        Fault fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
@@ -382,7 +382,7 @@ output decoder {{
 }};
 
 output exec {{
-    Fault *
+    Fault
     Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
     {
         return NoFault;
diff --git a/arch/alpha/isa/mem.isa b/arch/alpha/isa/mem.isa
index 33b7341ef..61d6ea8fa 100644
--- a/arch/alpha/isa/mem.isa
+++ b/arch/alpha/isa/mem.isa
@@ -173,12 +173,12 @@ def template LoadStoreDeclare {{
 
 
 def template InitiateAccDeclare {{
-    Fault * initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+    Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
 }};
 
 
 def template CompleteAccDeclare {{
-    Fault * completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
+    Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
 }};
 
 
@@ -208,12 +208,12 @@ def template LoadStoreConstructor {{
 
 
 def template EACompExecute {{
-    Fault *
+    Fault
     %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
                                    Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault * fault = NoFault;
+        Fault fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
@@ -230,12 +230,12 @@ def template EACompExecute {{
 }};
 
 def template LoadMemAccExecute {{
-    Fault *
+    Fault
     %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
                                    Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault * fault = NoFault;
+        Fault fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
@@ -257,11 +257,11 @@ def template LoadMemAccExecute {{
 
 
 def template LoadExecute {{
-    Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault * fault = NoFault;
+        Fault fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
@@ -283,11 +283,11 @@ def template LoadExecute {{
 
 
 def template LoadInitiateAcc {{
-    Fault * %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
+    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
                                       Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault * fault = NoFault;
+        Fault fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_src_decl)s;
@@ -304,11 +304,11 @@ def template LoadInitiateAcc {{
 
 
 def template LoadCompleteAcc {{
-    Fault * %(class_name)s::completeAcc(uint8_t *data,
+    Fault %(class_name)s::completeAcc(uint8_t *data,
                                       %(CPU_exec_context)s *xc,
                                       Trace::InstRecord *traceData) const
     {
-        Fault * fault = NoFault;
+        Fault fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_src_decl)s;
@@ -330,12 +330,12 @@ def template LoadCompleteAcc {{
 
 
 def template StoreMemAccExecute {{
-    Fault *
+    Fault
     %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
                                    Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault * fault = NoFault;
+        Fault fault = NoFault;
         uint64_t write_result = 0;
 
         %(fp_enable_check)s;
@@ -367,11 +367,11 @@ def template StoreMemAccExecute {{
 
 
 def template StoreExecute {{
-    Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault * fault = NoFault;
+        Fault fault = NoFault;
         uint64_t write_result = 0;
 
         %(fp_enable_check)s;
@@ -402,11 +402,11 @@ def template StoreExecute {{
 }};
 
 def template StoreInitiateAcc {{
-    Fault * %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
+    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
                                       Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault * fault = NoFault;
+        Fault fault = NoFault;
         uint64_t write_result = 0;
 
         %(fp_enable_check)s;
@@ -431,11 +431,11 @@ def template StoreInitiateAcc {{
 
 
 def template StoreCompleteAcc {{
-    Fault * %(class_name)s::completeAcc(uint8_t *data,
+    Fault %(class_name)s::completeAcc(uint8_t *data,
                                       %(CPU_exec_context)s *xc,
                                       Trace::InstRecord *traceData) const
     {
-        Fault * fault = NoFault;
+        Fault fault = NoFault;
         uint64_t write_result = 0;
 
         %(fp_enable_check)s;
@@ -457,11 +457,11 @@ def template StoreCompleteAcc {{
 
 
 def template MiscMemAccExecute {{
-    Fault * %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
+    Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
                                           Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault * fault = NoFault;
+        Fault fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
@@ -477,11 +477,11 @@ def template MiscMemAccExecute {{
 }};
 
 def template MiscExecute {{
-    Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault * fault = NoFault;
+        Fault fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
@@ -497,7 +497,7 @@ def template MiscExecute {{
 }};
 
 def template MiscInitiateAcc {{
-    Fault * %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
+    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
                                       Trace::InstRecord *traceData) const
     {
         panic("Misc instruction does not support split access method!");
@@ -507,7 +507,7 @@ def template MiscInitiateAcc {{
 
 
 def template MiscCompleteAcc {{
-    Fault * %(class_name)s::completeAcc(uint8_t *data,
+    Fault %(class_name)s::completeAcc(uint8_t *data,
                                       %(CPU_exec_context)s *xc,
                                       Trace::InstRecord *traceData) const
     {
diff --git a/arch/alpha/isa/unimp.isa b/arch/alpha/isa/unimp.isa
index ce8197708..de4ac3eaf 100644
--- a/arch/alpha/isa/unimp.isa
+++ b/arch/alpha/isa/unimp.isa
@@ -105,7 +105,7 @@ output decoder {{
 }};
 
 output exec {{
-    Fault *
+    Fault
     FailUnimplemented::execute(%(CPU_exec_context)s *xc,
                                Trace::InstRecord *traceData) const
     {
@@ -114,7 +114,7 @@ output exec {{
         return UnimplementedOpcodeFault;
     }
 
-    Fault *
+    Fault
     WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
                                Trace::InstRecord *traceData) const
     {
diff --git a/arch/alpha/isa/unknown.isa b/arch/alpha/isa/unknown.isa
index e7f8bc8db..4601b3684 100644
--- a/arch/alpha/isa/unknown.isa
+++ b/arch/alpha/isa/unknown.isa
@@ -36,7 +36,7 @@ output decoder {{
 }};
 
 output exec {{
-    Fault *
+    Fault
     Unknown::execute(%(CPU_exec_context)s *xc,
                      Trace::InstRecord *traceData) const
     {