diff options
| author | Steve Reinhardt <stever@eecs.umich.edu> | 2003-10-13 22:21:19 -0700 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2003-10-13 22:21:19 -0700 |
| commit | af5cdc1d8c42bd28472d1bd7126dd8af7d799aeb (patch) | |
| tree | 3e12401114dc5e3aa93dd8c4279e50329af2a9cc /arch/alpha | |
| parent | 35e5d907c46b945021c34f7d1b57a5c98189d566 (diff) | |
| download | gem5-af5cdc1d8c42bd28472d1bd7126dd8af7d799aeb.tar.xz | |
Rename CPU object to FullCPU
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
cpu/static_inst.hh:
CPU -> FullCPU
--HG--
extra : convert_revision : 2bed1ed9372ca9e33f7e391a1aa47bbc02675691
Diffstat (limited to 'arch/alpha')
| -rw-r--r-- | arch/alpha/isa_desc | 22 | ||||
| -rw-r--r-- | arch/alpha/isa_traits.hh | 2 |
2 files changed, 12 insertions, 12 deletions
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index c023405c8..e9b93a895 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -256,7 +256,7 @@ def template BasicDeclare {{ return fault; } - Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst, + Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst, Trace::InstRecord *traceData) { DynInst *memAccessObj __attribute__((unused)) = dynInst; @@ -320,7 +320,7 @@ declare {{ return No_Fault; } - Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst, + Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst, Trace::InstRecord *traceData) { return No_Fault; @@ -643,7 +643,7 @@ def template FloatingPointDeclare {{ return fault; } - Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst, + Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst, Trace::InstRecord *traceData) { Fault fault = No_Fault; @@ -701,7 +701,7 @@ def template FloatingPointDeclare {{ return fault; } - Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst, + Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst, Trace::InstRecord *traceData) { Fault fault = No_Fault; @@ -830,7 +830,7 @@ declare {{ Trace::InstRecord *traceData) { panic("attempt to execute eacomp"); } - Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst, + Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst, Trace::InstRecord *traceData) { panic("attempt to execute eacomp"); } }; @@ -852,7 +852,7 @@ declare {{ Trace::InstRecord *traceData) { panic("attempt to execute memacc"); } - Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst, + Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst, Trace::InstRecord *traceData) { panic("attempt to execute memacc"); } }; @@ -952,7 +952,7 @@ def template LoadStoreDeclare {{ return fault; } - Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst, + Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst, Trace::InstRecord *traceData) { DynInst *memAccessObj = dynInst; @@ -1019,7 +1019,7 @@ def template PrefetchDeclare {{ return No_Fault; } - Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst, + Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst, Trace::InstRecord *traceData) { Addr EA; @@ -1544,7 +1544,7 @@ declare {{ return Unimplemented_Opcode_Fault; } - Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst, + Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst, Trace::InstRecord *traceData) { // don't panic if this is a misspeculated instruction @@ -1594,7 +1594,7 @@ declare {{ return No_Fault; } - Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst, + Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst, Trace::InstRecord *traceData) { if (!xc->spec_mode && !warned) { @@ -1665,7 +1665,7 @@ declare {{ return Unimplemented_Opcode_Fault; } - Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst, + Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst, Trace::InstRecord *traceData) { // don't panic if this is a misspeculated instruction diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index 9840636e0..6b78722ad 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -33,7 +33,7 @@ #include "targetarch/faults.hh" #include "base/misc.hh" -class CPU; +class FullCPU; class IniFile; #define TARGET_ALPHA |