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author | Steve Reinhardt <stever@eecs.umich.edu> | 2003-10-18 21:21:14 -0700 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2003-10-18 21:21:14 -0700 |
commit | 83d32482dc126d028399ca6701642047f28276dd (patch) | |
tree | 737a9f3e2a6974a559046a0da03c5b6db2db7a26 /arch/alpha | |
parent | 1bebc1ab2f49af51cf899be6cb88409abbd81461 (diff) | |
download | gem5-83d32482dc126d028399ca6701642047f28276dd.tar.xz |
Add comment to elaborate on store-conditional result code (and remove
stale reference to machine.def).
arch/alpha/isa_desc:
Add comment describing store-conditional result code
cpu/exec_context.hh:
update comments
--HG--
extra : convert_revision : ac59e0ad7a9440cb6656617fdf05495b59c68f55
Diffstat (limited to 'arch/alpha')
-rw-r--r-- | arch/alpha/isa_desc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index e9b93a895..b5536525d 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -1808,11 +1808,19 @@ decode OPCODE default Unknown::unknown() { 0x2e: stl_c({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }}, {{ uint64_t tmp = Mem_write_result; + // see stq_c Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; }}, LOCKED); 0x2f: stq_c({{ EA = Rb + disp; }}, {{ Mem.uq = Ra; }}, {{ uint64_t tmp = Mem_write_result; + // If the write operation returns 0 or 1, then + // this was a conventional store conditional, + // and the value indicates the success/failure + // of the operation. If another value is + // returned, then this was a Turbolaser + // mailbox access, and we don't update the + // result register at all. Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; }}, LOCKED); } |