Support NNPC and branch instructions ... Outputs to decoder.cc correctly

Edits to the CPU model may still need to be made to handle branch likely insts...

arch/isa_parser.py:
    add a NNPC operand ...
arch/mips/isa/base.isa:
    change SPARC to MIPS
arch/mips/isa/decoder.isa:
    typo < to >=
arch/mips/isa/formats/basic.isa:
    spacing
arch/mips/isa/formats/branch.isa:
    add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
    support for NNPC and R31
arch/mips/isa_traits.hh:
    NNPC Addr variable

--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad

1 files changed, 10 insertions, 0 deletions

diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index 96d3e8438..606432e60 100755
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -1355,6 +1355,7 @@ class MemOperand(Operand):
     def makeAccSize(self):
         return self.size
 
+
 class NPCOperand(Operand):
     def makeConstructor(self):
         return ''
@@ -1365,6 +1366,15 @@ class NPCOperand(Operand):
     def makeWrite(self):
         return 'xc->setNextPC(%s);\n' % self.base_name
 
+class NNPCOperand(Operand):
+    def makeConstructor(self):
+        return ''
+
+    def makeRead(self):
+        return '%s = xc->readPC() + 8;\n' % self.base_name
+
+    def makeWrite(self):
+        return 'xc->setNextNPC(%s);\n' % self.base_name
 
 def buildOperandNameMap(userDict, lineno):
     global operandNameMap