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authorGabe Black <gblack@eecs.umich.edu>2006-02-19 03:20:05 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-02-19 03:20:05 -0500
commitf721a4d9adb0cbed48ef8f18dc7455a3ed8f5a9b (patch)
tree335e7c747799099b12b38c94eceb1fd7a49c7148 /arch/isa_parser.py
parented25d326174f8086a8224ecb9e798410db14cddb (diff)
parent14f2cdb1a14e9e6896939c210cdacef289d9c263 (diff)
downloadgem5-f721a4d9adb0cbed48ef8f18dc7455a3ed8f5a9b.tar.xz
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch arch/alpha/faults.hh: ur Using cleaned up fault class deiffinitions --HG-- extra : convert_revision : a600950d539be2be73358f072aa5426456bf3d2d
Diffstat (limited to 'arch/isa_parser.py')
-rwxr-xr-xarch/isa_parser.py4
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index 864a6a8a7..b92d267c9 100755
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -1149,10 +1149,6 @@ class Operand(object):
self.constructor = self.makeConstructor()
self.op_decl = self.makeDecl()
- if self.isMem():
- self.is_src = ''
- self.is_dest = ''
-
if self.is_src:
self.op_rd = self.makeRead()
self.op_src_decl = self.makeDecl()