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authorKevin Lim <ktlim@umich.edu>2006-02-16 11:55:28 -0500
committerKevin Lim <ktlim@umich.edu>2006-02-16 11:55:28 -0500
commit485568efa972db7fc27f34708d9bc3a2f19871de (patch)
tree36ce046052a69c7838d4afc50712883e5c7f33a3 /arch/isa_parser.py
parent2d04f186748c70b3d8afecd39b94436c33848d93 (diff)
downloadgem5-485568efa972db7fc27f34708d9bc3a2f19871de.tar.xz
Fixes to handle generating the initiateAcc and completeAcc functions a little more cleanly.
arch/alpha/isa/mem.isa: Avoid explicitly declaring the Mem variable. Instead break up the code blocks used to generate the initiate and complete functions. The templates reflect which operands need to be declared for each function (src, dest, or both). Loads use both the EA code and mem acc code for the initiate, and memacc code and postacc code for the complete. Stores use both the EA code and mem acc code for the initiate, and only post acc code for the complete. arch/isa_parser.py: Remove hack for mem ops. --HG-- extra : convert_revision : a367797a2cb698762bfc27be1da00bcbe9367150
Diffstat (limited to 'arch/isa_parser.py')
-rwxr-xr-xarch/isa_parser.py4
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index 96d3e8438..bcef77ddf 100755
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -1149,10 +1149,6 @@ class Operand(object):
self.constructor = self.makeConstructor()
self.op_decl = self.makeDecl()
- if self.isMem():
- self.is_src = ''
- self.is_dest = ''
-
if self.is_src:
self.op_rd = self.makeRead()
self.op_src_decl = self.makeDecl()