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authorRon Dreslinski <rdreslin@umich.edu>2006-01-31 12:12:49 -0500
committerRon Dreslinski <rdreslin@umich.edu>2006-01-31 12:12:49 -0500
commita1033448ead67ea2819d67609c0390aefc865b0f (patch)
tree07c968291776217ecebc763b4a828b500eb603cc /arch/isa_parser.py
parent0e79d188e1437d313f28bf6ee808b92ae0ce03a6 (diff)
downloadgem5-a1033448ead67ea2819d67609c0390aefc865b0f.tar.xz
Inital split up of the header files for the new memory system. Still need to fill in some of the include files, and other data types. But this will be the starting point.
mem/bus.hh: Inital crack at a bus object that has ports. Still need to clean up the include file issues. mem/mem_object.hh: Decleration of a base memory object. Derives from simobject and adds a function to get the port associated with the object. mem/packet.hh: Inital crack at the packet decleration. Still need to clean up the include file issues. mem/port.hh: Inital crack at the port decleration. Still need to clean up the include file issues. mem/request.hh: Inital crack at the request decleration. Still need to clean up the include file issues. --HG-- extra : convert_revision : f17967d430458f91866a4639ab0cab45d835bb55
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