Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs.

They are now accessed by calling readMiscReg()/setMiscReg() on the XC.  Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future).

arch/alpha/alpha_memory.cc:
    Change accesses to IPR to go through the XC.
arch/alpha/ev5.cc:
    Change accesses for IPRs to go through the misc regs.
arch/alpha/isa/decoder.isa:
    Change accesses to IPRs to go through the misc regs.  readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect().
arch/alpha/isa/fp.isa:
    Change accesses to IPRs and Fpcr to go through the misc regs.
arch/alpha/isa/main.isa:
    Add support for all misc regs being accessed through readMiscReg() and setMiscReg().  Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index.
arch/alpha/isa_traits.hh:
    Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs.
    Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect.  The latter are basically the original read/write IPR functions, while the former are normal reads/writes.

    The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs.
arch/alpha/stacktrace.cc:
cpu/simple/cpu.cc:
dev/sinic.cc:
    Change accesses to the IPRs to go through the XC.
arch/alpha/vtophys.cc:
    Change access to the IPR to go through the XC.
arch/isa_parser.py:
    Change generation of code for control registers to use the readMiscReg and setMiscReg functions.
base/remote_gdb.cc:
    Change accesses to the IPR to go through the XC.
cpu/exec_context.hh:
    Use the miscRegs to access the lock addr, lock flag, and other misc registers.
cpu/o3/alpha_cpu.hh:
cpu/simple/cpu.hh:
    Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions.
cpu/o3/alpha_cpu_impl.hh:
    Change accesses to the IPRs to go through the miscRegs.
    For now comment out some of the accesses to the misc regs until the proxy exec context is completed.
cpu/o3/alpha_dyn_inst.hh:
    Change accesses to misc regs to use readMiscReg and setMiscReg.
cpu/o3/alpha_dyn_inst_impl.hh:
    Remove old misc reg accessors.
cpu/o3/cpu.cc:
    Comment out old misc reg accesses until the proxy exec context is completed.
cpu/o3/cpu.hh:
    Change accesses to the misc regs.
cpu/o3/regfile.hh:
    Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg.  They are dummy functions for now until the proxy exec context is completed.
kern/kernel_stats.cc:
kern/system_events.cc:
    Have accesses to the IPRs go through the XC.
kern/tru64/tru64.hh:
    Have accesses to the misc regs use the new access methods.

--HG--
extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76

1 files changed, 4 insertions, 4 deletions

diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index 6508ca02a..5185ed573 100755
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -1263,10 +1263,10 @@ class ControlRegOperand(Operand):
     def makeConstructor(self):
         c = ''
         if self.is_src:
-            c += '\n\t_srcRegIdx[%d] = %s_DepTag;' % \
+            c += '\n\t_srcRegIdx[%d] = %s;' % \
                  (self.src_reg_idx, self.reg_spec)
         if self.is_dest:
-            c += '\n\t_destRegIdx[%d] = %s_DepTag;' % \
+            c += '\n\t_destRegIdx[%d] = %s;' % \
                  (self.dest_reg_idx, self.reg_spec)
         return c
 
@@ -1274,7 +1274,7 @@ class ControlRegOperand(Operand):
         bit_select = 0
         if (self.ctype == 'float' or self.ctype == 'double'):
             error(0, 'Attempt to read control register as FP')
-        base = 'xc->read%s()' % self.reg_spec
+        base = 'xc->readMiscReg(%s)' % self.reg_spec
         if self.size == self.dflt_size:
             return '%s = %s;\n' % (self.base_name, base)
         else:
@@ -1284,7 +1284,7 @@ class ControlRegOperand(Operand):
     def makeWrite(self):
         if (self.ctype == 'float' or self.ctype == 'double'):
             error(0, 'Attempt to write control register as FP')
-        wb = 'xc->set%s(%s);\n' % (self.reg_spec, self.base_name)
+        wb = 'xc->setMiscReg(%s, %s);\n' % (self.reg_spec, self.base_name)
         wb += 'if (traceData) { traceData->setData(%s); }' % \
               self.base_name
         return wb