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authorKorey Sewell <ksewell@umich.edu>2006-02-21 22:02:05 -0500
committerKorey Sewell <ksewell@umich.edu>2006-02-21 22:02:05 -0500
commita4799a89ded3b2ebddd682dbcb0f8d2dd968b68a (patch)
tree6464529eceafa3ed8e6b30e19e3e0cb216dc9113 /arch/mips/isa/base.isa
parent3f7979c99d8dc4f434e3daa2e179616f1669e16e (diff)
downloadgem5-a4799a89ded3b2ebddd682dbcb0f8d2dd968b68a.tar.xz
Renaming alpha files and changing some MIPS stuff to be more like Alpha version
SConscript: changed the alpha_memory.hh to memory.hh in SConscript arch/isa_parser.py: temporarily comment out o3 model arch/mips/isa/base.isa: arch/mips/isa_traits.cc: arch/mips/isa_traits.hh: Fix Up Base Class to mirror how Alpha generates StaticInsts arch/mips/faults.cc: MIPS fault.cc file arch/mips/faults.hh: MIPS fault.hh file --HG-- rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux_process.hh rename : arch/alpha/alpha_memory.cc => arch/alpha/memory.cc rename : arch/alpha/alpha_memory.hh => arch/alpha/memory.hh rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64_process.hh extra : convert_revision : f92d6e765ca96a8b952aef79ed119fa29464563b
Diffstat (limited to 'arch/mips/isa/base.isa')
-rw-r--r--arch/mips/isa/base.isa104
1 files changed, 64 insertions, 40 deletions
diff --git a/arch/mips/isa/base.isa b/arch/mips/isa/base.isa
index 846d161b9..49de59e55 100644
--- a/arch/mips/isa/base.isa
+++ b/arch/mips/isa/base.isa
@@ -7,57 +7,81 @@
//Outputs to decoder.hh
output header {{
- /**
- * Base class for all MIPS static instructions.
- */
- class MipsStaticInst : public StaticInst<MIPSISA>
+ /**
+ * Base class for all MIPS static instructions.
+ */
+ class MipsStaticInst : public StaticInst
+ {
+ protected:
+
+ /// Make MipsISA register dependence tags directly visible in
+ /// this class and derived classes. Maybe these should really
+ /// live here and not in the MipsISA namespace.
+ enum DependenceTags {
+ FP_Base_DepTag = MipsISA::FP_Base_DepTag,
+ Fpcr_DepTag = MipsISA::Fpcr_DepTag,
+ Uniq_DepTag = MipsISA::Uniq_DepTag,
+ IPR_Base_DepTag = MipsISA::IPR_Base_DepTag
+ };
+
+ // Constructor
+ MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : StaticInst(mnem, _machInst, __opClass)
{
- protected:
+ }
- // Constructor.
- MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
- : StaticInst<MIPSISA>(mnem, _machInst, __opClass)
- {
- }
+ /// Print a register name for disassembly given the unique
+ /// dependence tag number (FP or int).
+ void printReg(std::ostream &os, int reg) const;
- std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
- };
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
}};
//Ouputs to decoder.cc
output decoder {{
- std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ void MipsStaticInst::printReg(std::ostream &os, int reg) const
+ {
+ if (reg < FP_Base_DepTag) {
+ ccprintf(os, "r%d", reg);
+ }
+ else {
+ ccprintf(os, "f%d", reg - FP_Base_DepTag);
+ }
+ }
+
+ std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+
+ ccprintf(ss, "%-10s ", mnemonic);
+
+ // just print the first two source regs... if there's
+ // a third one, it's a read-modify-write dest (Rc),
+ // e.g. for CMOVxx
+ if(_numSrcRegs > 0)
+ {
+ printReg(ss, _srcRegIdx[0]);
+ }
+ if(_numSrcRegs > 1)
{
- std::stringstream ss;
-
- ccprintf(ss, "%-10s ", mnemonic);
-
- // just print the first two source regs... if there's
- // a third one, it's a read-modify-write dest (Rc),
- // e.g. for CMOVxx
- if(_numSrcRegs > 0)
- {
- printReg(ss, _srcRegIdx[0]);
- }
- if(_numSrcRegs > 1)
- {
- ss << ",";
- printReg(ss, _srcRegIdx[1]);
- }
-
- // just print the first dest... if there's a second one,
- // it's generally implicit
- if(_numDestRegs > 0)
- {
- if(_numSrcRegs > 0)
- ss << ",";
- printReg(ss, _destRegIdx[0]);
- }
-
- return ss.str();
+ ss << ",";
+ printReg(ss, _srcRegIdx[1]);
}
+ // just print the first dest... if there's a second one,
+ // it's generally implicit
+ if(_numDestRegs > 0)
+ {
+ if(_numSrcRegs > 0)
+ ss << ",";
+ printReg(ss, _destRegIdx[0]);
+ }
+
+ return ss.str();
+ }
+
}};