Support NNPC and branch instructions ... Outputs to decoder.cc correctly

Edits to the CPU model may still need to be made to handle branch likely insts...

arch/isa_parser.py:
    add a NNPC operand ...
arch/mips/isa/base.isa:
    change SPARC to MIPS
arch/mips/isa/decoder.isa:
    typo < to >=
arch/mips/isa/formats/basic.isa:
    spacing
arch/mips/isa/formats/branch.isa:
    add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
    support for NNPC and R31
arch/mips/isa_traits.hh:
    NNPC Addr variable

--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad

1 files changed, 1 insertions, 1 deletions

diff --git a/arch/mips/isa/base.isa b/arch/mips/isa/base.isa
index 99fa302c0..db37cf49c 100644
--- a/arch/mips/isa/base.isa
+++ b/arch/mips/isa/base.isa
@@ -16,7 +16,7 @@ output header {{
 
                 // Constructor.
                 MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
-                    : StaticInst<SPARCISA>(mnem, _machInst, __opClass)
+                    : StaticInst<MIPSISA>(mnem, _machInst, __opClass)
                 {
                 }