diff options
author | Korey Sewell <ksewell@umich.edu> | 2006-03-19 13:40:03 -0500 |
---|---|---|
committer | Korey Sewell <ksewell@umich.edu> | 2006-03-19 13:40:03 -0500 |
commit | b3464ef18061626c096c96d952971e61de97938b (patch) | |
tree | c3dae7020f8ec40cfc8a291cd01cc3679f9cb850 /arch/mips/isa/base.isa | |
parent | e6bc492554408e89d7ced523c66991665126dc29 (diff) | |
download | gem5-b3464ef18061626c096c96d952971e61de97938b.tar.xz |
support for unaligned memory access
arch/mips/isa/base.isa:
disassembly fixes
arch/mips/isa/decoder.isa:
support for unaligned loads/stores
arch/mips/isa_traits.hh:
edit Syscall Reg values
arch/mips/linux_process.cc:
call writevFunc on writev syscall
--HG--
extra : convert_revision : 4aea6d069bd7ba0e83b23d2d85c50d68532f0454
Diffstat (limited to 'arch/mips/isa/base.isa')
-rw-r--r-- | arch/mips/isa/base.isa | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/mips/isa/base.isa b/arch/mips/isa/base.isa index 89837c136..139a6d876 100644 --- a/arch/mips/isa/base.isa +++ b/arch/mips/isa/base.isa @@ -67,12 +67,11 @@ output decoder {{ ccprintf(ss, "%-10s ", mnemonic); if(_numDestRegs > 0){ - if(_numSrcRegs > 0) - ss << ","; printReg(ss, _destRegIdx[0]); } if(_numSrcRegs > 0) { + ss << ","; printReg(ss, _srcRegIdx[0]); } @@ -82,8 +81,8 @@ output decoder {{ } - if(mnemonic == "sll"){ - ccprintf(ss," %d",SA); + if(mnemonic == "sll" || mnemonic == "sra"){ + ccprintf(ss,", %d",SA); } return ss.str(); |