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| author | Korey Sewell <ksewell@umich.edu> | 2006-05-08 03:59:40 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2006-05-08 03:59:40 -0400 |
| commit | a4ed65d0fa0a66d069f70a01c0caeb215e7ec760 (patch) | |
| tree | f9e6e1ed7fb447a190399af1977d01c6afeb1cdf /arch/mips/isa/bitfields.isa | |
| parent | 1047215ee58bf2b3df0b5e72f1e97da3891e3ed2 (diff) | |
| download | gem5-a4ed65d0fa0a66d069f70a01c0caeb215e7ec760.tar.xz | |
Start working on more complex FP tests
Debug FP instructions to handle these FP insts
arch/mips/isa/bitfields.isa:
add Bitfield for Floating Point Condition Codes
arch/mips/isa/decoder.isa:
Follow instruction naming style with FP single insts
Send the float value to the convert&round functions in single FP
add ll inst support
add 'token' sc support
arch/mips/isa_traits.cc:
Add SINGLE->WORD, WORD->SINGLE, & WORD->DOUBLE conversions
arch/mips/regfile.hh:
update header files
arch/mips/regfile/float_regfile.hh:
Add more FP registers
--HG--
rename : arch/mips/int_regfile.hh => arch/mips/regfile/int_regfile.hh
rename : arch/mips/misc_regfile.hh => arch/mips/regfile/misc_regfile.hh
extra : convert_revision : 92faf0bfd8542ade762ac569ec158d198f6a9c7e
Diffstat (limited to 'arch/mips/isa/bitfields.isa')
| -rw-r--r-- | arch/mips/isa/bitfields.isa | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/mips/isa/bitfields.isa b/arch/mips/isa/bitfields.isa index eb917595c..e1124a591 100644 --- a/arch/mips/isa/bitfields.isa +++ b/arch/mips/isa/bitfields.isa @@ -39,7 +39,6 @@ def bitfield FT <20:16>; def bitfield FS <15:11>; def bitfield FD <10:6>; -def bitfield CC <20:18>; def bitfield ND <17:17>; def bitfield TF <16:16>; def bitfield MOVCI <16:16>; @@ -48,6 +47,10 @@ def bitfield SRL <21:21>; def bitfield SRLV < 6: 6>; def bitfield SA <10: 6>; +// Floating Point Condition Codes +def bitfield CC <10:8>; +def bitfield BRANCH_CC <20:18>; + // CP0 Register Select def bitfield SEL < 2: 0>; |