updated MIPS ISA files .... all files should be able to compile/build with MIPS option except isa_traits.*

which I need to update the misc. regfile accesses

arch/mips/faults.cc:
arch/mips/faults.hh:
    alpha to mips
arch/mips/isa/base.isa:
    add includes
arch/mips/isa/bitfields.isa:
    more bitfields
arch/mips/isa/decoder.isa:
    lots o' lots o' lots o' changes!!!!
arch/mips/isa/formats.isa:
    include cop0.isa
arch/mips/isa/formats/basic.isa:
    fix faults
arch/mips/isa/formats/branch.isa:
arch/mips/isa/formats/fp.isa:
arch/mips/isa/formats/int.isa:
arch/mips/isa/formats/mem.isa:
arch/mips/isa/formats/noop.isa:
arch/mips/isa/formats/trap.isa:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
arch/mips/isa/formats/util.isa:
arch/mips/isa/operands.isa:
arch/mips/isa_traits.cc:
arch/mips/linux_process.cc:
    merge MIPS-specific comilable/buidable files code into multiarch
arch/mips/isa_traits.hh:
    merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have
    need to be recoded and everything should build then ...
arch/mips/stacktrace.hh:
    file copied over

--HG--
extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f

1 files changed, 5 insertions, 0 deletions

diff --git a/arch/mips/isa/bitfields.isa b/arch/mips/isa/bitfields.isa
index 3a01b64ee..58d487ad2 100644
--- a/arch/mips/isa/bitfields.isa
+++ b/arch/mips/isa/bitfields.isa
@@ -33,10 +33,12 @@ def bitfield INTIMM	<15: 0>; // integer immediate (literal)
 
 // Floating-point operate format
 def bitfield FMT      <25:21>;
+def bitfield FR       <25:21>;
 def bitfield FT	      <20:16>;
 def bitfield FS	      <15:11>;
 def bitfield FD	      <10:6>;
 
+def bitfield CC       <20:18>;
 def bitfield ND       <17:17>;
 def bitfield TF       <16:16>;
 def bitfield MOVCI    <16:16>;
@@ -45,6 +47,9 @@ def bitfield SRL      <21:21>;
 def bitfield SRLV     < 6: 6>;
 def bitfield SA       <10: 6>;
 
+// CP0 Register Select
+def bitfield SEL       < 2: 0>;
+
 // Interrupts
 def bitfield SC       < 5: 5>;