Hand merge. Stuff probably doesn't compile.

--HG--
rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux/process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux/process.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64/process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64/process.hh
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : 7d1efcedd708815d985a951f6f010fbd83dc27e8

1 files changed, 67 insertions, 0 deletions

diff --git a/arch/mips/isa/bitfields.isa b/arch/mips/isa/bitfields.isa
new file mode 100644
index 000000000..58d487ad2
--- /dev/null
+++ b/arch/mips/isa/bitfields.isa
@@ -0,0 +1,67 @@
+// -*- mode:c++ -*-
+
+////////////////////////////////////////////////////////////////////
+//
+// Bitfield definitions.
+//
+
+def bitfield OPCODE     <31:26>;
+def bitfield OPCODE_HI  <31:29>;
+def bitfield OPCODE_LO  <28:26>;
+
+def bitfield REGIMM      <20:16>;
+def bitfield REGIMM_HI   <20:19>;
+def bitfield REGIMM_LO   <18:16>;
+
+def bitfield FUNCTION      < 5: 0>;
+def bitfield FUNCTION_HI   < 5: 3>;
+def bitfield FUNCTION_LO   < 2: 0>;
+
+// Integer operate format
+def bitfield RT	      <20:16>;
+def bitfield RT_HI    <20:19>;
+def bitfield RT_LO    <18:16>;
+
+def bitfield RS	      <25:21>;
+def bitfield RS_MSB   <25:25>;
+def bitfield RS_HI    <25:24>;
+def bitfield RS_LO    <23:21>;
+
+def bitfield RD	      <15:11>;
+
+def bitfield INTIMM	<15: 0>; // integer immediate (literal)
+
+// Floating-point operate format
+def bitfield FMT      <25:21>;
+def bitfield FR       <25:21>;
+def bitfield FT	      <20:16>;
+def bitfield FS	      <15:11>;
+def bitfield FD	      <10:6>;
+
+def bitfield CC       <20:18>;
+def bitfield ND       <17:17>;
+def bitfield TF       <16:16>;
+def bitfield MOVCI    <16:16>;
+def bitfield MOVCF    <16:16>;
+def bitfield SRL      <21:21>;
+def bitfield SRLV     < 6: 6>;
+def bitfield SA       <10: 6>;
+
+// CP0 Register Select
+def bitfield SEL       < 2: 0>;
+
+// Interrupts
+def bitfield SC       < 5: 5>;
+
+// Branch format
+def bitfield OFFSET <15: 0>; // displacement
+
+// Jmp format
+def bitfield JMPTARG	<25: 0>;
+def bitfield HINT	<10: 6>;
+
+def bitfield SYSCALLCODE <25: 6>;
+def bitfield TRAPCODE    <15:13>;
+
+// M5 instructions
+def bitfield M5FUNC <7:0>;