load/store instruction format ... now generates load/store code

and breaks it into a separate EA and MemAccess templated
from how the Alpha ARch. was coded to do the same thing.

arch/mips/isa/bitfields.isa:
    comment change
arch/mips/isa/decoder.isa:
    re-structuring of load/store instruction definitions
arch/mips/isa/formats/mem.isa:
    Define LoadMemory & Store Memory formats
    Use style of formatting & base class similar to what was used for ALPHA
arch/mips/isa/formats/util.isa:
    Insert LoadStoreBase function here from alpha/arch/isa/mem.isa
arch/mips/isa/operands.isa:
    change shw->sh and uhw->uh

--HG--
extra : convert_revision : 5d85f15f4a600dd4c473a3b4a170ba39cf07fc8a

1 files changed, 3 insertions, 1 deletions

diff --git a/arch/mips/isa/bitfields.isa b/arch/mips/isa/bitfields.isa
index bead9c151..532b3793a 100644
--- a/arch/mips/isa/bitfields.isa
+++ b/arch/mips/isa/bitfields.isa
@@ -1,3 +1,5 @@
+// -*- mode:c++ -*-
+
 ////////////////////////////////////////////////////////////////////
 //
 // Bitfield definitions.
@@ -41,7 +43,7 @@ def bitfield SC       < 5: 5>;
 // Branch format
 def bitfield OFFSET <15: 0>; // displacement
 
-// Memory-format jumps
+// Jmp format
 def bitfield JMPTARG	<25: 0>;
 def bitfield JMPHINT	<10: 6>;