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| author | Korey Sewell <ksewell@umich.edu> | 2006-04-12 03:44:45 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2006-04-12 03:44:45 -0400 |
| commit | 4fe89f7232202040b8b8fcea2461e5ae6be2d739 (patch) | |
| tree | 71d4f25c95264ac9e9d47bb624cb4d8ddadbe078 /arch/mips/isa/decoder.isa | |
| parent | da7990ab337699ae788809ddaea5ba5c363e0015 (diff) | |
| download | gem5-4fe89f7232202040b8b8fcea2461e5ae6be2d739.tar.xz | |
add OSFlags struct to AlphaISA/MipsISA namespace. The OS classes then use these OSFlags to access architecture-specific AND OS-specific
flags for their functions (e.g. OS::OSFlags::TG_MAP_ANONYMOUS)...
arch/alpha/tru64/process.cc:
sim/syscall_emul.hh:
Add OSFlags to code
arch/mips/isa/decoder.isa:
slight decoder changes (more stylistic then anything)
arch/mips/isa/formats/util.isa:
spacing
arch/mips/isa_traits.hh:
add OSFlags struct to MipsISA namespace. The OS classes then use these OSFlags to access architecture-specific and OS-specific
flags for their functions
kern/linux/linux.hh:
remove constant placement ... define OSFlags in linux.hh
kern/tru64/tru64.hh:
define OSFlags in tru64
--HG--
extra : convert_revision : 59be1036eb439ca4ea1eea1d3b52e508023de6c9
Diffstat (limited to 'arch/mips/isa/decoder.isa')
| -rw-r--r-- | arch/mips/isa/decoder.isa | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa index 35e5fa75b..ffedfbca8 100644 --- a/arch/mips/isa/decoder.isa +++ b/arch/mips/isa/decoder.isa @@ -143,9 +143,11 @@ decode OPCODE_HI default Unknown::unknown() { }}); 0x1: multu({{ - int64_t temp1 = Rs.uw * Rt.uw; - xc->setMiscReg(Hi,temp1<63:32>); - xc->setMiscReg(Lo,temp1<31:0>); + uint64_t temp1 = Rs.uw * Rt.uw; + uint32_t hi_val = temp1<63:32>; + uint32_t lo_val = temp1<31:0>; + xc->setMiscReg(Hi,hi_val); + xc->setMiscReg(Lo,lo_val); }}); 0x2: div({{ @@ -154,8 +156,8 @@ decode OPCODE_HI default Unknown::unknown() { }}); 0x3: divu({{ - xc->setMiscReg(Hi,Rs.uw % Rt.uw); - xc->setMiscReg(Lo,Rs.uw / Rt.uw); + xc->setMiscReg(Hi,Rs.uw % Rt.uw); + xc->setMiscReg(Lo,Rs.uw / Rt.uw); }}); } } |