diff options
| author | Korey Sewell <ksewell@umich.edu> | 2006-03-12 05:58:28 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2006-03-12 05:58:28 -0500 |
| commit | 57d53f8a9d738b43e0de41a70813e3a6de8d4dfb (patch) | |
| tree | 2bd45bf1d4a23ca8696b76fbffff3754dd244d4a /arch/mips/isa/decoder.isa | |
| parent | 18ba0f85486f0dd919064ba2b0ed8c53a7861298 (diff) | |
| parent | 4d19bbeeebd026b0aab52e381ee77e4141ed9dd1 (diff) | |
| download | gem5-57d53f8a9d738b43e0de41a70813e3a6de8d4dfb.tar.xz | |
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem
--HG--
extra : convert_revision : b101fa550567d5a9f5de6c2d8c3f67829ae050c1
Diffstat (limited to 'arch/mips/isa/decoder.isa')
| -rw-r--r-- | arch/mips/isa/decoder.isa | 59 |
1 files changed, 18 insertions, 41 deletions
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa index 3f054f6a5..ac97241ed 100644 --- a/arch/mips/isa/decoder.isa +++ b/arch/mips/isa/decoder.isa @@ -20,8 +20,8 @@ decode OPCODE_HI default Unknown::unknown() { 0x0: decode FUNCTION_LO { 0x1: decode MOVCI { format BasicOp { - 0: movf({{ if (xc->readMiscReg(FPCR,0) != CC) Rd = Rs}}); - 1: movt({{ if (xc->readMiscReg(FPCR,0) == CC) Rd = Rs}}); + 0: movf({{ if (xc->readMiscReg(FPCR) != CC) Rd = Rs}}); + 1: movt({{ if (xc->readMiscReg(FPCR) == CC) Rd = Rs}}); } } @@ -31,15 +31,10 @@ decode OPCODE_HI default Unknown::unknown() { //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." 0x0: decode RS { - 0x0: decode RT default BasicOp::sll({{ Rd = Rt.uw << SA; }}) { - 0x0: decode RD{ - 0x0: decode HINT { - 0x0:nop({{}}); //really sll r0,r0,0 - 0x1:ssnop({{}});//really sll r0,r0,1 - 0x3:ehb({{}}); //really sll r0,r0,3 - } - } - } + 0x0: sll({{ Rd = Rt.uw << SA; }}); + //0x0:nop({{ ; }}); //really sll r0,r0,0 + // 0x1:ssnop({{ ; }});//really sll r0,r0,1 + // 0x3:ehb({{ ; }}); //really sll r0,r0,3 } 0x2: decode SRL { @@ -283,55 +278,37 @@ decode OPCODE_HI default Unknown::unknown() { 0x0: decode SC { 0x0: dvpe({{ - int idx; - int sel; - getMiscRegIdx(MVPControl,idx,sel); - Rt.sw = xc->readMiscReg(idx,sel); - xc->setMiscReg(idx,sel); + Rt.sw = xc->readMiscReg(MVPControl); + xc->setMiscReg(MVPControl,0); }}); 0x1: evpe({{ - int idx; - int sel; - getMiscRegIdx(MVPControl,idx,sel); - Rt.sw = xc->readMiscReg(idx,sel); - xc->setMiscReg(idx,sel,1); + Rt.sw = xc->readMiscReg(MVPControl); + xc->setMiscReg(MVPControl,1); }}); } 0x1: decode SC { 0x0: dmt({{ - int idx; - int sel; - getMiscRegIdx(VPEControl,idx,sel); - Rt.sw = xc->readMiscReg(idx,sel); - xc->setMiscReg(idx,sel); + Rt.sw = xc->readMiscReg(VPEControl); + xc->setMiscReg(VPEControl,0); }}); 0x1: emt({{ - int idx; - int sel; - getMiscRegIdx(VPEControl,idx,sel); - Rt.sw = xc->readMiscReg(idx,sel); - xc->setMiscReg(idx,sel,1); + Rt.sw = xc->readMiscReg(VPEControl); + xc->setMiscReg(VPEControl,1); }}); } 0xC: decode SC { 0x0: di({{ - int idx; - int sel; - getMiscRegIdx(Status,idx,sel); - Rt.sw = xc->readMiscReg(idx,sel); - xc->setMiscReg(idx,sel); + Rt.sw = xc->readMiscReg(Status); + xc->setMiscReg(Status,0); }}); 0x1: ei({{ - int idx; - int sel; - getMiscRegIdx(Status,idx,sel); - Rt.sw = xc->readMiscReg(idx,sel); - xc->setMiscReg(idx,sel,1); + Rt.sw = xc->readMiscReg(Status); + xc->setMiscReg(Status,1); }}); } } |