Minor Sconscript edit ... mips decoder changes ... initialize NNPC and output fault name in simple cpu

SConscript:
    Separate Alpha EIO from syscall building for other architectures
arch/isa_specific.hh:
    change MIPS constant to 34k
arch/mips/isa/decoder.isa:
    Allow sll,ssnop,nop, and ehb to be determined through decoder using
    the different types of default cases
arch/mips/isa/formats/branch.isa:
    Delete debug code
arch/mips/isa/formats/noop.isa:
    add a Nop format
arch/mips/isa_traits.hh:
    use constants instead of enums
arch/mips/process.cc:
    point to the correct header file
cpu/simple/cpu.cc:
    Output the actual fault name
sim/process.cc:
    Inititalize NNPC

--HG--
extra : convert_revision : adb0026dfad25b14c98fb03c98bfe9c681bba6f8

1 files changed, 11 insertions, 5 deletions

diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index ac97241ed..93e7238f8 100644
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -30,11 +30,17 @@ decode OPCODE_HI default Unknown::unknown() {
                     //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields
                     //are used to distinguish among the SLL, NOP, SSNOP and EHB functions."
 
-                    0x0: decode RS {
-                        0x0: sll({{ Rd = Rt.uw << SA; }});
-                        //0x0:nop({{ ; }});  //really sll r0,r0,0
-                        //	    0x1:ssnop({{ ; }});//really sll r0,r0,1
-                        //    0x3:ehb({{ ; }});  //really sll r0,r0,3
+                    0x0: decode RS  {
+                        0x0: decode RT {
+                                 0x0: decode RD default Nop::nop() {
+                                  0x0: decode SA {
+                                      0x1: ssnop({{ ; }});  //really sll r0,r0,1
+                                      0x3: ehb({{ ; }});  //really sll r0,r0,3
+                                  }
+                             }
+                        }
+
+                      default: sll({{ Rd = Rt.uw << SA; }});
                     }
 
                     0x2: decode SRL {