Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5

into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

cpu/simple/cpu.cc:
    Hand Merge

--HG--
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : bf664b092f993d0f4675ce8e7df13645a920c1f4

1 files changed, 11 insertions, 1 deletions

diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index 9994acd0b..3f054f6a5 100644
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -30,7 +30,17 @@ decode OPCODE_HI default Unknown::unknown() {
                     //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields
                     //are used to distinguish among the SLL, NOP, SSNOP and EHB functions."
 
-                    0x0: sll({{ Rd = Rt.uw << SA; }});
+                    0x0: decode RS {
+                        0x0: decode RT default BasicOp::sll({{ Rd = Rt.uw << SA; }}) {
+                            0x0: decode RD{
+                                0x0: decode HINT {
+                                    0x0:nop({{}});  //really sll r0,r0,0
+                                    0x1:ssnop({{}});//really sll r0,r0,1
+                                    0x3:ehb({{}});  //really sll r0,r0,3
+                                }
+                            }
+                        }
+                    }
 
                     0x2: decode SRL {
                         0: srl({{ Rd = Rt.uw >> SA; }});