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authorKorey Sewell <ksewell@umich.edu>2006-03-12 05:57:34 -0500
committerKorey Sewell <ksewell@umich.edu>2006-03-12 05:57:34 -0500
commit4d19bbeeebd026b0aab52e381ee77e4141ed9dd1 (patch)
tree9255f7e8dfc49bc62940f6a79ffc36546c5e4f92 /arch/mips/isa/decoder.isa
parent0cbb43ebb1f115f844ee0deab8a965add19a2775 (diff)
downloadgem5-4d19bbeeebd026b0aab52e381ee77e4141ed9dd1.tar.xz
MIPS is back to compiling and building now!
arch/alpha/isa_traits.hh: used for SimpleCPU instead of explicitly calling the namespace we declare in isa_traits.hhs so other archs. can use SimpleCPU arch/mips/SConscript: dont include common_syscall or tru64 arch/mips/faults.cc: arch/mips/faults.hh: arch/mips/isa/formats/unimp.isa: arch/mips/isa/formats/unknown.isa: Change Faults to new format arch/mips/isa/decoder.isa: Fix readMiscReg access Made change so that you cant explicitly tell if a instruction nop,ehb,or ssnop... These are all variants of the sll instruction so I may need to make a separte class of instructions to handle thse better arch/mips/isa/includes.isa: add isa_traits.hh and MipsISA included into every auto-gen file arch/mips/isa_traits.cc: create copyMiscRegs function... delete useless code arch/mips/isa_traits.hh: clean up for build arch/mips/linux_process.cc: mem is now getMemPort(), linux process objects now take in a system argument arch/mips/linux_process.hh: new argument for linux process arch/mips/process.cc: add system arch/mips/process.hh: add system variable cpu/cpu_exec_context.cc: Change AlphaISA to TheISA cpu/exec_context.hh: add readNextNPC and setNextNPC functions cpu/simple/cpu.cc: include isa_traits for namespace declariation cpu/simple/cpu.hh: PC & NPC access/modify functions arch/mips/utility.hh: file needed for compile --HG-- extra : convert_revision : 29a327e79c51c6174a6e526aa68c7aab7e7eb535
Diffstat (limited to 'arch/mips/isa/decoder.isa')
-rw-r--r--arch/mips/isa/decoder.isa59
1 files changed, 18 insertions, 41 deletions
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index 3f054f6a5..ac97241ed 100644
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -20,8 +20,8 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode FUNCTION_LO {
0x1: decode MOVCI {
format BasicOp {
- 0: movf({{ if (xc->readMiscReg(FPCR,0) != CC) Rd = Rs}});
- 1: movt({{ if (xc->readMiscReg(FPCR,0) == CC) Rd = Rs}});
+ 0: movf({{ if (xc->readMiscReg(FPCR) != CC) Rd = Rs}});
+ 1: movt({{ if (xc->readMiscReg(FPCR) == CC) Rd = Rs}});
}
}
@@ -31,15 +31,10 @@ decode OPCODE_HI default Unknown::unknown() {
//are used to distinguish among the SLL, NOP, SSNOP and EHB functions."
0x0: decode RS {
- 0x0: decode RT default BasicOp::sll({{ Rd = Rt.uw << SA; }}) {
- 0x0: decode RD{
- 0x0: decode HINT {
- 0x0:nop({{}}); //really sll r0,r0,0
- 0x1:ssnop({{}});//really sll r0,r0,1
- 0x3:ehb({{}}); //really sll r0,r0,3
- }
- }
- }
+ 0x0: sll({{ Rd = Rt.uw << SA; }});
+ //0x0:nop({{ ; }}); //really sll r0,r0,0
+ // 0x1:ssnop({{ ; }});//really sll r0,r0,1
+ // 0x3:ehb({{ ; }}); //really sll r0,r0,3
}
0x2: decode SRL {
@@ -283,55 +278,37 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode SC {
0x0: dvpe({{
- int idx;
- int sel;
- getMiscRegIdx(MVPControl,idx,sel);
- Rt.sw = xc->readMiscReg(idx,sel);
- xc->setMiscReg(idx,sel);
+ Rt.sw = xc->readMiscReg(MVPControl);
+ xc->setMiscReg(MVPControl,0);
}});
0x1: evpe({{
- int idx;
- int sel;
- getMiscRegIdx(MVPControl,idx,sel);
- Rt.sw = xc->readMiscReg(idx,sel);
- xc->setMiscReg(idx,sel,1);
+ Rt.sw = xc->readMiscReg(MVPControl);
+ xc->setMiscReg(MVPControl,1);
}});
}
0x1: decode SC {
0x0: dmt({{
- int idx;
- int sel;
- getMiscRegIdx(VPEControl,idx,sel);
- Rt.sw = xc->readMiscReg(idx,sel);
- xc->setMiscReg(idx,sel);
+ Rt.sw = xc->readMiscReg(VPEControl);
+ xc->setMiscReg(VPEControl,0);
}});
0x1: emt({{
- int idx;
- int sel;
- getMiscRegIdx(VPEControl,idx,sel);
- Rt.sw = xc->readMiscReg(idx,sel);
- xc->setMiscReg(idx,sel,1);
+ Rt.sw = xc->readMiscReg(VPEControl);
+ xc->setMiscReg(VPEControl,1);
}});
}
0xC: decode SC {
0x0: di({{
- int idx;
- int sel;
- getMiscRegIdx(Status,idx,sel);
- Rt.sw = xc->readMiscReg(idx,sel);
- xc->setMiscReg(idx,sel);
+ Rt.sw = xc->readMiscReg(Status);
+ xc->setMiscReg(Status,0);
}});
0x1: ei({{
- int idx;
- int sel;
- getMiscRegIdx(Status,idx,sel);
- Rt.sw = xc->readMiscReg(idx,sel);
- xc->setMiscReg(idx,sel,1);
+ Rt.sw = xc->readMiscReg(Status);
+ xc->setMiscReg(Status,1);
}});
}
}