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author | Korey Sewell <ksewell@umich.edu> | 2006-02-18 23:17:45 -0500 |
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committer | Korey Sewell <ksewell@umich.edu> | 2006-02-18 23:17:45 -0500 |
commit | a48c24b61eedf580645ff0294b225d1e69a9444b (patch) | |
tree | 6c5337e0e6d801a4b5831f56b74293806b61a767 /arch/mips/isa/formats/branch.isa | |
parent | bd175809286e8da64176da977aeb27fc6ff6d272 (diff) | |
download | gem5-a48c24b61eedf580645ff0294b225d1e69a9444b.tar.xz |
Support NNPC and branch instructions ... Outputs to decoder.cc correctly
Edits to the CPU model may still need to be made to handle branch likely insts...
arch/isa_parser.py:
add a NNPC operand ...
arch/mips/isa/base.isa:
change SPARC to MIPS
arch/mips/isa/decoder.isa:
typo < to >=
arch/mips/isa/formats/basic.isa:
spacing
arch/mips/isa/formats/branch.isa:
add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
support for NNPC and R31
arch/mips/isa_traits.hh:
NNPC Addr variable
--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
Diffstat (limited to 'arch/mips/isa/formats/branch.isa')
-rw-r--r-- | arch/mips/isa/formats/branch.isa | 24 |
1 files changed, 16 insertions, 8 deletions
diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa index d9dd433e3..1f7a6f330 100644 --- a/arch/mips/isa/formats/branch.isa +++ b/arch/mips/isa/formats/branch.isa @@ -45,12 +45,12 @@ output header {{ { protected: /// target address (signed) Displacement . - int32_t targetOffset; + int32_t disp; /// Constructor. Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : PCDependentDisassembly(mnem, _machInst, __opClass), - targetOffset(OFFSET << 2) + disp(OFFSET << 2) { } @@ -67,12 +67,12 @@ output header {{ { protected: /// target address (signed) Displacement . - int32_t targetOffset; + int32_t disp; /// Constructor. Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : PCDependentDisassembly(mnem, _machInst, __opClass), - targetOffset(OFFSET << 2) + disp(OFFSET << 2) { } @@ -255,9 +255,12 @@ def format Branch(code,*flags) {{ #Add Link Code if Link instruction strlen = len(name) if name[strlen-2:] == 'al': - code += 'R31 = NPC + 8;\n' + code += 'R31 = NPC + 4;\n' - code += '\nif (cond) NPC = NPC + disp;\n'; + # condition code + code += 'if (cond) {' + code += ' NPC = NPC + disp;\n' + code += ' NNPC = NNPC + disp;\n } \n' iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), ('IsDirectControl', 'IsCondControl')) @@ -267,15 +270,20 @@ def format Branch(code,*flags) {{ exec_output = BasicExecute.subst(iop) }}; + def format BranchLikely(code,*flags) {{ code = 'bool cond;\n\t\t\t' + code #Add Link Code if Link instruction strlen = len(name) if name[strlen-3:] == 'all': - code += 'R31 = NPC + 8;\n' + code += 'R31 = NPC + 4;\n' + + #condition code + code += 'if (cond) {' + code += ' NPC = NPC + disp;\n' + code += ' NNPC = NNPC + disp;\n } \n' - code = '\t\t\tif (cond) NPC = NPC + disp;\n'; iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), ('IsDirectControl', 'IsCondControl','IsCondDelaySlot')) |