Merge zizzer:/bk/multiarch

into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch

--HG--
extra : convert_revision : 2bfc19cfa186776ff94440b01ea51f520f61234f

1 files changed, 78 insertions, 0 deletions

diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa
new file mode 100644
index 000000000..5ed5237c5
--- /dev/null
+++ b/arch/mips/isa/formats/mem.isa
@@ -0,0 +1,78 @@
+////////////////////////////////////////////////////////////////////
+//
+// Mem instructions
+//
+
+output header {{
+        /**
+         * Base class for integer operations.
+         */
+        class Mem : public MipsStaticInst
+        {
+                protected:
+
+                /// Constructor
+                Mem(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+}};
+
+output decoder {{
+        std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+                return "Disassembly of integer instruction\n";
+        }
+}};
+
+def template MemExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                //Attempt to execute the instruction
+                try
+                {
+
+                        %(op_decl)s;
+                        %(op_rd)s;
+                        ea_code
+                        %(code)s;
+                }
+                //If we have an exception for some reason,
+                //deal with it
+                catch(MipsException except)
+                {
+                        //Deal with exception
+                        return No_Fault;
+                }
+
+                //Write the resulting state to the execution context
+                %(op_wb)s;
+
+                return No_Fault;
+        }
+}};
+
+// Primary format for integer operate instructions:
+def format Mem(code, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+        iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        exec_output = MemExecute.subst(iop)
+        exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;');
+}};
+
+def format Cas(code, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+        iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        exec_output = MemExecute.subst(iop)
+        exec_output.replace('ea_code', 'EA = R1;');
+}};