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| author | Korey Sewell <ksewell@umich.edu> | 2006-04-10 12:37:15 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2006-04-10 12:37:15 -0400 |
| commit | f51656498ea4c3418499f25e5a7a24b4c71be122 (patch) | |
| tree | f54ef3c2ec601519e0cc98f007705e56a4b20dc0 /arch/mips/isa/formats/mem.isa | |
| parent | ae1a95ed9c9aa2b3c97272570575345dc3c37799 (diff) | |
| parent | 4f430e9ab56443e822171b7881f4d50475dbaf25 (diff) | |
| download | gem5-f51656498ea4c3418499f25e5a7a24b4c71be122.tar.xz | |
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips
arch/mips/isa/formats/mem.isa:
Filled in Split-Memory Access Code
arch/mips/isa_traits.hh:
Leave IntRegFile as an array instead of class with member functions
mem/page_table.cc:
take out NO ALIGN FAULT page table access code for now... No need to messs up what works
--HG--
extra : convert_revision : cbf1cce9145daf9ee9ceabc9080271ddb0561489
Diffstat (limited to 'arch/mips/isa/formats/mem.isa')
| -rw-r--r-- | arch/mips/isa/formats/mem.isa | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa index 404aa1ee1..df1dca4e1 100644 --- a/arch/mips/isa/formats/mem.isa +++ b/arch/mips/isa/formats/mem.isa @@ -446,6 +446,14 @@ def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, exec_template_base = 'Store') }}; +def format UnalignedStore(memacc_code, postacc_code, + ea_code = {{ EA = Rb + disp; }}, + mem_flags = [], inst_flags = []) {{ + (header_output, decoder_output, decode_block, exec_output) = \ + LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, + postacc_code, exec_template_base = 'Store') +}}; + //FP loads are offloaded to these formats for now ... def format LoadMemory2(ea_code = {{ EA = Rs + disp; }}, memacc_code = {{ }}, mem_flags = [], inst_flags = []) {{ |