Finally MIPS does hello world!

arch/mips/isa/bitfields.isa:
    add RS_SRL bitfield ...these must be set to 0 for a SRL instruction
arch/mips/isa/decoder.isa:
    Make unimplemented instructions Fail instead of just Warn
    Edits to SRA & SRAV instructions
    Implement CFC1 instructions
    Unaligned Memory Access Support (Maybe Not fully functional yet)
    Enforce a more strict decode policy (in terms of different bitfields set to 0 on certain instructions)
arch/mips/isa/formats/branch.isa:
    Fix disassembly
arch/mips/isa/formats/int.isa:
    Add sign extend Immediate and zero extend Immediate to Int class.
    Probably a bit unnecessary in the long run since these manipulations could
    be done in the actually instruction instead of keep a int value
arch/mips/isa/formats/mem.isa:
    Comment/Remove out split-memory access code... revisit this after SimpleCPU works
arch/mips/isa/formats/unimp.isa:
    Add inst2string function to Unimplemented panic. PRints out the instruction
    binary to help in debuggin
arch/mips/isa/formats/unknown.isa:
    define inst2string function , use in unknown disassembly and panic function
arch/mips/isa/operands.isa:
    Make "Mem" default to a unsigned word since this is MIPS32
arch/mips/isa_traits.hh:
    change return values to 32 instead of 64
arch/mips/linux_process.cc:
    assign some syscalls to the right functions
cpu/static_inst.hh:
    more debug functions for MIPS (these will be move to the mips directory soon)
mem/page_table.cc:
mem/page_table.hh:
    toward a better implementation for unaligned memory access
mem/request.hh:
    NO ALIGN FAULT flag added to support unaligned memory access
sim/syscall_emul.cc:
    additional SyscallVerbose comments

--HG--
extra : convert_revision : 1987d80c9f4ede507f1f0148435e0bee97d2428c

1 files changed, 14 insertions, 102 deletions

diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa
index 8a07e63d4..a42976331 100644
--- a/arch/mips/isa/formats/mem.isa
+++ b/arch/mips/isa/formats/mem.isa
@@ -199,23 +199,8 @@ def template LoadMemAccExecute {{
     %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
                                    Trace::InstRecord *traceData) const
     {
-        Addr EA;
         Fault fault = NoFault;
-
-        %(fp_enable_check)s;
-        %(op_decl)s;
-        %(op_rd)s;
-        EA = xc->getEA();
-
-        if (fault == NoFault) {
-            fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
-            %(code)s;
-        }
-
-        if (fault == NoFault) {
-            %(op_wb)s;
-        }
-
+        //Fill in Code for Out-of-Order CPUs
         return fault;
     }
 }};
@@ -251,18 +236,8 @@ def template LoadInitiateAcc {{
     Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
                                       Trace::InstRecord *traceData) const
     {
-        Addr EA;
         Fault fault = NoFault;
-
-        %(fp_enable_check)s;
-        %(op_src_decl)s;
-        %(op_rd)s;
-        %(ea_code)s;
-
-        if (fault == NoFault) {
-            fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
-        }
-
+        //Fill in Code for Out-of-Order CPUs
         return fault;
     }
 }};
@@ -274,21 +249,7 @@ def template LoadCompleteAcc {{
                                       Trace::InstRecord *traceData) const
     {
         Fault fault = NoFault;
-
-        %(fp_enable_check)s;
-        %(op_src_decl)s;
-        %(op_dest_decl)s;
-
-        memcpy(&Mem, data, sizeof(Mem));
-
-        if (fault == NoFault) {
-            %(memacc_code)s;
-        }
-
-        if (fault == NoFault) {
-            %(op_wb)s;
-        }
-
+        //Fill in Code for Out-of-Order CPUs
         return fault;
     }
 }};
@@ -299,33 +260,8 @@ def template StoreMemAccExecute {{
     %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
                                    Trace::InstRecord *traceData) const
     {
-        Addr EA;
         Fault fault = NoFault;
-        uint64_t write_result = 0;
-
-        %(fp_enable_check)s;
-        %(op_decl)s;
-        %(op_rd)s;
-        EA = xc->getEA();
-
-        if (fault == NoFault) {
-            %(code)s;
-        }
-
-        if (fault == NoFault) {
-            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, &write_result);
-            if (traceData) { traceData->setData(Mem); }
-        }
-
-        if (fault == NoFault) {
-            %(postacc_code)s;
-        }
-
-        if (fault == NoFault) {
-            %(op_wb)s;
-        }
-
+        //Fill in Code for Out-of-Order CPUs
         return fault;
     }
 }};
@@ -370,26 +306,8 @@ def template StoreInitiateAcc {{
     Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
                                       Trace::InstRecord *traceData) const
     {
-        Addr EA;
         Fault fault = NoFault;
-        uint64_t write_result = 0;
-
-        %(fp_enable_check)s;
-        %(op_src_decl)s;
-        %(op_dest_decl)s;
-        %(op_rd)s;
-        %(ea_code)s;
-
-        if (fault == NoFault) {
-            %(memacc_code)s;
-        }
-
-        if (fault == NoFault) {
-            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, &write_result);
-            if (traceData) { traceData->setData(Mem); }
-        }
-
+        //Fill in Code for Out-of-Order CPUs
         return fault;
     }
 }};
@@ -401,21 +319,7 @@ def template StoreCompleteAcc {{
                                       Trace::InstRecord *traceData) const
     {
         Fault fault = NoFault;
-        uint64_t write_result = 0;
-
-        %(fp_enable_check)s;
-        %(op_dest_decl)s;
-
-        memcpy(&write_result, data, sizeof(write_result));
-
-        if (fault == NoFault) {
-            %(postacc_code)s;
-        }
-
-        if (fault == NoFault) {
-            %(op_wb)s;
-        }
-
+        //Fill in Code for Out-of-Order CPUs
         return fault;
     }
 }};
@@ -448,6 +352,14 @@ def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
                       exec_template_base = 'Store')
 }};
 
+def format UnalignedStore(memacc_code, postacc_code,
+                     ea_code = {{ EA = Rb + disp; }},
+                     mem_flags = [], inst_flags = []) {{
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+                      postacc_code, exec_template_base = 'Store')
+}};
+
 //FP loads are offloaded to these formats for now ...
 def format LoadMemory2(ea_code = {{ EA = Rs + disp; }}, memacc_code = {{ }},
                       mem_flags = [], inst_flags = []) {{