updated MIPS ISA files .... all files should be able to compile/build with MIPS option except isa_traits.*

which I need to update the misc. regfile accesses

arch/mips/faults.cc:
arch/mips/faults.hh:
    alpha to mips
arch/mips/isa/base.isa:
    add includes
arch/mips/isa/bitfields.isa:
    more bitfields
arch/mips/isa/decoder.isa:
    lots o' lots o' lots o' changes!!!!
arch/mips/isa/formats.isa:
    include cop0.isa
arch/mips/isa/formats/basic.isa:
    fix faults
arch/mips/isa/formats/branch.isa:
arch/mips/isa/formats/fp.isa:
arch/mips/isa/formats/int.isa:
arch/mips/isa/formats/mem.isa:
arch/mips/isa/formats/noop.isa:
arch/mips/isa/formats/trap.isa:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
arch/mips/isa/formats/util.isa:
arch/mips/isa/operands.isa:
arch/mips/isa_traits.cc:
arch/mips/linux_process.cc:
    merge MIPS-specific comilable/buidable files code into multiarch
arch/mips/isa_traits.hh:
    merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have
    need to be recoded and everything should build then ...
arch/mips/stacktrace.hh:
    file copied over

--HG--
extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f

1 files changed, 46 insertions, 23 deletions

diff --git a/arch/mips/isa/formats/util.isa b/arch/mips/isa/formats/util.isa
index c06877b35..db4bf204a 100644
--- a/arch/mips/isa/formats/util.isa
+++ b/arch/mips/isa/formats/util.isa
@@ -1,29 +1,6 @@
 // -*- mode:c++ -*-
 
 let {{
-def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
-    # Declare basic control transfer w/o link (i.e. link reg is R31)
-    nolink_code = 'NPC = %s;\n' % npc_expr
-    nolink_iop = InstObjParams(name, Name, base_class,
-                               CodeBlock(nolink_code), flags)
-    header_output = BasicDeclare.subst(nolink_iop)
-    decoder_output = BasicConstructor.subst(nolink_iop)
-    exec_output = BasicExecute.subst(nolink_iop)
-
-    # Generate declaration of '*AndLink' version, append to decls
-    link_code = 'Ra = NPC & ~3;\n' + nolink_code
-    link_iop = InstObjParams(name, Name + 'AndLink', base_class,
-                             CodeBlock(link_code), flags)
-    header_output += BasicDeclare.subst(link_iop)
-    decoder_output += BasicConstructor.subst(link_iop)
-    exec_output += BasicExecute.subst(link_iop)
-
-    # need to use link_iop for the decode template since it is expecting
-    # the shorter version of class_name (w/o "AndLink")
-
-    return (header_output, decoder_output,
-            JumpOrBranchDecode.subst(nolink_iop), exec_output)
-
 def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                   postacc_code = '', base_class = 'Memory',
                   decode_template = BasicDecode, exec_template_base = ''):
@@ -116,10 +93,56 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
 
 output exec {{
 
+using namespace MipsISA;
+
+
     /// CLEAR ALL CPU INST/EXE HAZARDS
     inline void
     clear_exe_inst_hazards()
     {
         //CODE HERE
     }
+
+
+    /// Check "FP enabled" machine status bit.  Called when executing any FP
+    /// instruction in full-system mode.
+    /// @retval Full-system mode: NoFault if FP is enabled, FenFault
+    /// if not.  Non-full-system mode: always returns NoFault.
+#if FULL_SYSTEM
+    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
+    {
+        Fault fault = NoFault;	// dummy... this ipr access should not fault
+        if (!Mips34k::ICSR_FPE(xc->readIpr(MipsISA::IPR_ICSR, fault))) {
+            fault = FloatEnableFault;
+        }
+        return fault;
+    }
+#else
+    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
+    {
+        return NoFault;
+    }
+#endif
+
+    double convert_and_round(float w, int x, int y, int z)
+    {
+        double temp = .34000;
+
+        return temp;
+    }
+
+    enum FPTypes{
+        FP_SINGLE,
+        FP_DOUBLE,
+        FP_LONG,
+        FP_PS_LO,
+        FP_PS_HI,
+        FP_WORD,
+        RND_NEAREST,
+        RND_ZERO,
+        RND_UP,
+        RND_DOWN
+    };
 }};
+
+