MIPS generates ISA code through scons '.../decoder.cc'!!!

Now, must create g++ compilable code ...

arch/mips/isa/decoder.isa:
    missing a '}' ... edited a few instruction decodings ...
arch/mips/isa/formats.isa:
    rearranged #include
arch/mips/isa/formats/branch.isa:
    add Branch Likely  and Unconditional format
arch/mips/isa/formats/int.isa:
    move OperateNopCheckDecode template to another file ...
arch/mips/isa/formats/noop.isa:
    change Alpha to Mips in noop.isa

--HG--
extra : convert_revision : 4bf955fa6dffbbc99fb95fee7878f691e3df5424

3 files changed, 32 insertions, 83 deletions

diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa
index c7c97c2c8..75e7830d0 100644
--- a/arch/mips/isa/formats/branch.isa
+++ b/arch/mips/isa/formats/branch.isa
@@ -61,8 +61,7 @@ output header {{
     };
 
     /**
-     * Base class for branches (PC-relative control transfers),
-     * conditional or unconditional.
+     * Base class for branch likely branches (PC-relative control transfers),
      */
     class BranchLikely : public PCDependentDisassembly
     {
@@ -206,14 +205,21 @@ output decoder {{
     }
 }};
 
+
 def template JumpOrBranchDecode {{
     return (RD == 0)
         ? (StaticInst<MipsISA> *)new %(class_name)s(machInst)
         : (StaticInst<MipsISA> *)new %(class_name)sAndLink(machInst);
 }};
 
-def format Branch(code) {{
-    code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
+def format Branch(code,*flags) {{
+    code = 'bool cond;\n' + code + '\n'
+
+    if flags == 'IsLink':
+        code += 'R31 = NPC + 8\n'
+
+    code += '\nif (cond) NPC = NPC + disp;\n';
+
     iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
                         ('IsDirectControl', 'IsCondControl'))
     header_output = BasicDeclare.subst(iop)
@@ -222,28 +228,29 @@ def format Branch(code) {{
     exec_output = BasicExecute.subst(iop)
 }};
 
-
-def format BranchLikely(code) {{
+def format BranchLikely(code,*flags) {{
     code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
+
+    if flags == 'IsLink':
+        code += 'R31 = NPC + 8\n'
+
     iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
-                        ('IsDirectControl', 'IsCondControl'))
+                        ('IsDirectControl', 'IsCondControl','IsCondDelaySlot'))
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)
     exec_output = BasicExecute.subst(iop)
 }};
 
-
-def format UncondBranch(*flags) {{
-    flags += ('IsUncondControl', 'IsDirectControl')
-    (header_output, decoder_output, decode_block, exec_output) = \
-        UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
+def format Unconditional(code,*flags) {{
+    iop = InstObjParams(name, Name, 'Jump', CodeBlock(code),
+                        ('IsIndirectControl', 'IsUncondControl'))
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
 }};
 
-def format Jump(*flags) {{
-    flags += ('IsUncondControl', 'IsIndirectControl')
-    (header_output, decoder_output, decode_block, exec_output) = \
-        UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
-}};
+
 
 
diff --git a/arch/mips/isa/formats/int.isa b/arch/mips/isa/formats/int.isa
index 982992b41..cf06741a1 100644
--- a/arch/mips/isa/formats/int.isa
+++ b/arch/mips/isa/formats/int.isa
@@ -53,18 +53,6 @@ output decoder {{
 }};
 
 
-// integer & FP operate instructions use Rd as dest, so check for
-// Rd == 0 to detect nops
-def template OperateNopCheckDecode {{
- {
-     MipsStaticInst *i = new %(class_name)s(machInst);
-     if (RD == 0) {
-         i = makeNop(i);
-     }
-     return i;
- }
-}};
-
 //Used by decoder.isa
 def format IntOp(code, *opt_flags) {{
         orig_code = code
diff --git a/arch/mips/isa/formats/noop.isa b/arch/mips/isa/formats/noop.isa
index 6d45ba9b6..d366461e2 100644
--- a/arch/mips/isa/formats/noop.isa
+++ b/arch/mips/isa/formats/noop.isa
@@ -1,50 +1,4 @@
-////////////////////////////////////////////////////////////////////
-//
-// Noop instruction
-//
-
-output header {{
-        /**
-         * Base class for integer operations.
-         */
-        class Noop : public MipsStaticInst
-        {
-                protected:
-
-                /// Constructor
-                Noop(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
-                {
-                }
-
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-        };
-}};
-
-output decoder {{
-        std::string Noop::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-        {
-                return "Disassembly of integer instruction\n";
-        }
-}};
-
-def template NoopExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
-        {
-                //Nothing to see here, move along
-                return No_Fault;
-        }
-}};
-
-// Primary format for integer operate instructions:
-def format Noop(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = NoopExecute.subst(iop)
-}};
+// -*- mode:c++ -*-
 
 ////////////////////////////////////////////////////////////////////
 //
@@ -55,7 +9,7 @@ output header {{
     /**
      * Static instruction class for no-ops.  This is a leaf class.
      */
-    class Nop : public AlphaStaticInst
+    class Nop : public MipsStaticInst
     {
         /// Disassembly of original instruction.
         const std::string originalDisassembly;
@@ -63,7 +17,7 @@ output header {{
       public:
         /// Constructor
         Nop(const std::string _originalDisassembly, MachInst _machInst)
-            : AlphaStaticInst("nop", _machInst, No_OpClass),
+            : MipsStaticInst("nop", _machInst, No_OpClass),
               originalDisassembly(_originalDisassembly)
         {
             flags[IsNop] = true;
@@ -92,10 +46,10 @@ output decoder {{
     /// Helper function for decoding nops.  Substitute Nop object
     /// for original inst passed in as arg (and delete latter).
     inline
-    AlphaStaticInst *
-    makeNop(AlphaStaticInst *inst)
+    MipsStaticInst *
+    makeNop(MipsStaticInst *inst)
     {
-        AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
+        MipsStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
         delete inst;
         return nop;
     }
@@ -113,7 +67,7 @@ output exec {{
 // Rc == 31 to detect nops
 def template OperateNopCheckDecode {{
  {
-     AlphaStaticInst *i = new %(class_name)s(machInst);
+     MipsStaticInst *i = new %(class_name)s(machInst);
      if (RC == 31) {
          i = makeNop(i);
      }
@@ -124,7 +78,7 @@ def template OperateNopCheckDecode {{
 
 // Like BasicOperate format, but generates NOP if RC/FC == 31
 def format BasicOperateWithNopCheck(code, *opt_args) {{
-    iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
+    iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code),
                         opt_args)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)