MIPS Compiles scons/MIPS_SE/arch/mips/decoder.do!!!!!!

arch/mips/faults.hh:
    remove nonsense
arch/mips/isa/base.isa:
    define R31
arch/mips/isa/bitfields.isa:
    forgotten bitfields
arch/mips/isa/decoder.isa:
    INT64 -> int64_t
arch/mips/isa/formats.isa:
    fix comments
arch/mips/isa/formats/branch.isa:
    Branch -> BranchLikely
    RB -> RT
arch/mips/isa/formats/fp.isa:
    Make FP ops generates
arch/mips/isa/formats/mem.isa:
    RA,RB -> RS,RT
arch/mips/isa/formats/noop.isa:
    Rc -> Rd
arch/mips/isa/formats/util.isa:
    forgot brace and semicolon
arch/mips/isa/includes.isa:
    remove unnecessary files
arch/mips/isa_traits.hh:
    spacing
cpu/static_inst.hh:
    add cond_delay_slot flag

--HG--
extra : convert_revision : 3bc7353b437f9a764e85cc462bed86c9d654eb37

5 files changed, 18 insertions, 59 deletions

diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa
index fc207fd3f..c896e9b2d 100644
--- a/arch/mips/isa/formats/branch.isa
+++ b/arch/mips/isa/formats/branch.isa
@@ -70,7 +70,7 @@ output header {{
         int32_t disp;
 
         /// Constructor.
-        Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
+        BranchLikely(const char *mnem, MachInst _machInst, OpClass __opClass)
             : PCDependentDisassembly(mnem, _machInst, __opClass),
               disp(OFFSET << 2)
         {
@@ -243,7 +243,7 @@ output decoder {{
             ss << ",";
         }
 
-        ccprintf(ss, "(r%d)", RB);
+        ccprintf(ss, "(r%d)", RT);
 
         return ss.str();
     }
diff --git a/arch/mips/isa/formats/fp.isa b/arch/mips/isa/formats/fp.isa
index 23fcbaa67..7dd1e8442 100644
--- a/arch/mips/isa/formats/fp.isa
+++ b/arch/mips/isa/formats/fp.isa
@@ -1,3 +1,5 @@
+// -*- mode:c++ -*-
+
 ////////////////////////////////////////////////////////////////////
 //
 // Floating Point operate instructions
@@ -5,7 +7,7 @@
 
 output header {{
         /**
-         * Base class for integer operations.
+         * Base class for FP operations.
          */
         class FPOp : public MipsStaticInst
         {
@@ -70,62 +72,19 @@ def template FloatingPointExecute {{
 }};
 
 // Primary format for integer operate instructions:
-def format FloatOp(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        checkPriv = (code.find('checkPriv') != -1)
-        code.replace('checkPriv', '')
-        if checkPriv:
-                code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
-        else:
-                code.replace('checkPriv;', '')
-        for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
-                       ('xvValue', '0'), ('xcValue', '0')):
-                code.replace(marker, value)
-        iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+def format FloatOp(code, *flags) {{
+        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = FloatingPointExecute.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
 }};
 
 // Primary format for integer operate instructions:
-def format Float64Op(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        checkPriv = (code.find('checkPriv') != -1)
-        code.replace('checkPriv', '')
-        if checkPriv:
-                code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
-        else:
-                code.replace('checkPriv;', '')
-        for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
-                       ('xvValue', '0'), ('xcValue', '0')):
-                code.replace(marker, value)
-        iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = FloatingPointExecute.subst(iop)
-}};
-
-// Primary format for integer operate instructions:
-def format FPOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
-        orig_code = code
-
-        cblk = CodeBlock(code)
-        checkPriv = (code.find('checkPriv') != -1)
-        code.replace('checkPriv', '')
-        if checkPriv:
-                code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
-        else:
-                code.replace('checkPriv;', '')
-        for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
-                       ('xvValue', xvValue), ('xcValue', xcValue)):
-                code.replace(marker, value)
-        iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+def format Float64Op(code, *flags) {{
+        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = IntegerExecute.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
 }};
diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa
index 134548746..fcdb577c6 100644
--- a/arch/mips/isa/formats/mem.isa
+++ b/arch/mips/isa/formats/mem.isa
@@ -70,7 +70,7 @@ output decoder {{
     Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     {
         return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
-                        flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
+                        flags[IsFloating] ? 'f' : 'r', RS, JMPTARG, RT);
     }
 
 }};
diff --git a/arch/mips/isa/formats/noop.isa b/arch/mips/isa/formats/noop.isa
index d366461e2..05c5ac10f 100644
--- a/arch/mips/isa/formats/noop.isa
+++ b/arch/mips/isa/formats/noop.isa
@@ -63,12 +63,12 @@ output exec {{
     }
 }};
 
-// integer & FP operate instructions use Rc as dest, so check for
-// Rc == 31 to detect nops
+// integer & FP operate instructions use RT as dest, so check for
+// RT == 0 to detect nops
 def template OperateNopCheckDecode {{
  {
      MipsStaticInst *i = new %(class_name)s(machInst);
-     if (RC == 31) {
+     if (RD == 0) {
          i = makeNop(i);
      }
      return i;
diff --git a/arch/mips/isa/formats/util.isa b/arch/mips/isa/formats/util.isa
index f0671726c..c06877b35 100644
--- a/arch/mips/isa/formats/util.isa
+++ b/arch/mips/isa/formats/util.isa
@@ -122,4 +122,4 @@ output exec {{
     {
         //CODE HERE
     }
-}
+}};