updated MIPS ISA files .... all files should be able to compile/build with MIPS option except isa_traits.*

which I need to update the misc. regfile accesses

arch/mips/faults.cc:
arch/mips/faults.hh:
    alpha to mips
arch/mips/isa/base.isa:
    add includes
arch/mips/isa/bitfields.isa:
    more bitfields
arch/mips/isa/decoder.isa:
    lots o' lots o' lots o' changes!!!!
arch/mips/isa/formats.isa:
    include cop0.isa
arch/mips/isa/formats/basic.isa:
    fix faults
arch/mips/isa/formats/branch.isa:
arch/mips/isa/formats/fp.isa:
arch/mips/isa/formats/int.isa:
arch/mips/isa/formats/mem.isa:
arch/mips/isa/formats/noop.isa:
arch/mips/isa/formats/trap.isa:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
arch/mips/isa/formats/util.isa:
arch/mips/isa/operands.isa:
arch/mips/isa_traits.cc:
arch/mips/linux_process.cc:
    merge MIPS-specific comilable/buidable files code into multiarch
arch/mips/isa_traits.hh:
    merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have
    need to be recoded and everything should build then ...
arch/mips/stacktrace.hh:
    file copied over

--HG--
extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f

10 files changed, 172 insertions, 122 deletions

diff --git a/arch/mips/isa/formats/basic.isa b/arch/mips/isa/formats/basic.isa
index 3b62aa5c3..c02af7ddc 100644
--- a/arch/mips/isa/formats/basic.isa
+++ b/arch/mips/isa/formats/basic.isa
@@ -31,14 +31,14 @@ def template BasicConstructor {{
 def template BasicExecute {{
         Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
         {
-                Fault fault = No_Fault;
+                Fault fault = NoFault;
 
                 %(fp_enable_check)s;
                 %(op_decl)s;
                 %(op_rd)s;
                 %(code)s;
 
-                if(fault == No_Fault)
+                if(fault == NoFault)
                 {
                     %(op_wb)s;
                 }
diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa
index c896e9b2d..0d2ad7855 100644
--- a/arch/mips/isa/formats/branch.isa
+++ b/arch/mips/isa/formats/branch.isa
@@ -7,6 +7,9 @@
 
 output header {{
 
+#include <iostream>
+    using namespace std;
+
     /**
      * Base class for instructions whose disassembly is not purely a
      * function of the machine instruction (i.e., it depends on the
@@ -52,6 +55,10 @@ output header {{
             : PCDependentDisassembly(mnem, _machInst, __opClass),
               disp(OFFSET << 2)
         {
+            //If Bit 17 is 1 then Sign Extend
+            if ( (disp & 0x00020000) > 0  ) {
+                disp |= 0xFFFE0000;
+            }
         }
 
         Addr branchTarget(Addr branchPC) const;
@@ -74,6 +81,7 @@ output header {{
             : PCDependentDisassembly(mnem, _machInst, __opClass),
               disp(OFFSET << 2)
         {
+
         }
 
         Addr branchTarget(Addr branchPC) const;
@@ -93,11 +101,13 @@ output header {{
         /// Displacement to target address (signed).
         int32_t disp;
 
+        uint32_t target;
+
       public:
         /// Constructor
         Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
             : PCDependentDisassembly(mnem, _machInst, __opClass),
-              disp(OFFSET)
+              disp(JMPTARG << 2)
         {
         }
 
@@ -159,23 +169,17 @@ output decoder {{
         // either a source (the condition for conditional
         // branches) or a destination (the link reg for
         // unconditional branches)
-        if (_numSrcRegs > 0) {
+        if (_numSrcRegs == 1) {
             printReg(ss, _srcRegIdx[0]);
             ss << ",";
-        }
-        else if (_numDestRegs > 0) {
-            printReg(ss, _destRegIdx[0]);
+        } else if(_numSrcRegs == 2) {
+            printReg(ss, _srcRegIdx[0]);
             ss << ",";
-        }
-
-#ifdef SS_COMPATIBLE_DISASSEMBLY
-        if (_numSrcRegs == 0 && _numDestRegs == 0) {
-            printReg(ss, 31);
+            printReg(ss, _srcRegIdx[1]);
             ss << ",";
         }
-#endif
 
-        Addr target = pc + 4 + disp;
+        Addr target = pc + 8 + disp;
 
         std::string str;
         if (symtab && symtab->findSymbol(target, str))
@@ -206,13 +210,6 @@ output decoder {{
             ss << ",";
         }
 
-#ifdef SS_COMPATIBLE_DISASSEMBLY
-        if (_numSrcRegs == 0 && _numDestRegs == 0) {
-            printReg(ss, 31);
-            ss << ",";
-        }
-#endif
-
         Addr target = pc + 4 + disp;
 
         std::string str;
@@ -231,20 +228,25 @@ output decoder {{
 
         ccprintf(ss, "%-10s ", mnemonic);
 
-#ifdef SS_COMPATIBLE_DISASSEMBLY
-        if (_numDestRegs == 0) {
-            printReg(ss, 31);
-            ss << ",";
-        }
-#endif
-
-        if (_numDestRegs > 0) {
-            printReg(ss, _destRegIdx[0]);
+        if ( mnemonic == "jal" ) {
+            Addr npc = pc + 4;
+            ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp);
+        } else if (_numSrcRegs == 0) {
+            std::string str;
+            if (symtab && symtab->findSymbol(disp, str))
+                ss << str;
+            else
+                ccprintf(ss, "0x%x", disp);
+        } else if (_numSrcRegs == 1) {
+             printReg(ss, _srcRegIdx[0]);
+        } else if(_numSrcRegs == 2) {
+            printReg(ss, _srcRegIdx[0]);
             ss << ",";
+            printReg(ss, _srcRegIdx[1]);
+        } else {
+            panic(">= 3 Source Registers!!!");
         }
 
-        ccprintf(ss, "(r%d)", RT);
-
         return ss.str();
     }
 }};
@@ -253,16 +255,18 @@ def format Branch(code,*flags) {{
     #Add Link Code if Link instruction
     strlen = len(name)
     if name[strlen-2:] == 'al':
-        code += 'R31 = NNPC;\n'
+        code += 'r31 = NNPC;\n'
 
     #Condition code
     code = 'bool cond;\n' + code
     code += 'if (cond) {\n'
-    #code += '//NPC=NPC: just placeholder to force parser to writeback NPC\n'
-    #code += '  NPC = NPC; \n'
     code += '  NNPC = NPC + disp;\n'
+    code += '} else {\n'
+    code += '  NNPC = NNPC;\n'
     code += '} \n'
 
+    code += 'cout << hex << "NPC: " << NPC << " + " << disp << " = " << NNPC << endl;'
+
     iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
                         ('IsDirectControl', 'IsCondControl'))
 
@@ -277,13 +281,11 @@ def format BranchLikely(code,*flags) {{
     #Add Link Code if Link instruction
     strlen = len(name)
     if name[strlen-3:] == 'all':
-        code += 'R31 = NNPC;\n'
+        code += 'r31 = NNPC;\n'
 
     #Condition code
     code = 'bool cond;\n' + code
     code += 'if (cond) {'
-    #code += '//NPC=NPC: just placeholder to force parser to writeback NPC\n'
-    #code += 'NPC = NPC; \n'
     code += 'NNPC = NPC + disp;\n'
     code += '} \n'
 
@@ -300,8 +302,11 @@ def format BranchLikely(code,*flags) {{
 def format Jump(code,*flags) {{
     #Add Link Code if Link instruction
     strlen = len(name)
-    if strlen >= 3 and name[2:3] == 'al':
-            code = 'R31 = NNPC;\n' + code
+    if strlen > 1 and name[1:] == 'al':
+            code = 'r31 = NNPC;\n' + code
+
+    #code += 'if(NNPC == 0x80000638) { NNPC = r31; cout << "SKIPPING JUMP TO SIM_GET_MEM_CONF" << endl;}'
+    #code += 'target = NNPC;'
 
     iop = InstObjParams(name, Name, 'Jump', CodeBlock(code),\
                         ('IsIndirectControl', 'IsUncondControl'))
diff --git a/arch/mips/isa/formats/fp.isa b/arch/mips/isa/formats/fp.isa
index 7dd1e8442..34b71acf7 100644
--- a/arch/mips/isa/formats/fp.isa
+++ b/arch/mips/isa/formats/fp.isa
@@ -29,47 +29,6 @@ output decoder {{
         }
 }};
 
-def template FloatingPointExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
-        {
-                //These are set to constants when the execute method
-                //is generated
-                bool useCc = ;
-                bool checkPriv = ;
-
-                //Attempt to execute the instruction
-                try
-                {
-                        checkPriv;
-
-                        %(op_decl)s;
-                        %(op_rd)s;
-                        %(code)s;
-                }
-                //If we have an exception for some reason,
-                //deal with it
-                catch(MipsException except)
-                {
-                        //Deal with exception
-                        return No_Fault;
-                }
-
-                //Write the resulting state to the execution context
-                %(op_wb)s;
-                if(useCc)
-                {
-                        xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63);
-                        xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0);
-                        xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue;
-                        xc->regs.miscRegFile.ccrFields.iccFields.c = icValue;
-                        xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31);
-                        xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0);
-                        xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue;
-                        xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue;
-                }
-                return No_Fault;
-        }
-}};
 
 // Primary format for integer operate instructions:
 def format FloatOp(code, *flags) {{
diff --git a/arch/mips/isa/formats/int.isa b/arch/mips/isa/formats/int.isa
index cf06741a1..a47844bee 100644
--- a/arch/mips/isa/formats/int.isa
+++ b/arch/mips/isa/formats/int.isa
@@ -7,6 +7,8 @@
 
 //Outputs to decoder.hh
 output header {{
+#include <iostream>
+    using namespace std;
         /**
          * Base class for integer operations.
          */
@@ -26,15 +28,24 @@ output header {{
         class IntImmOp : public MipsStaticInst
         {
                 protected:
-                uint16_t imm;
+
+                int32_t imm;
 
                 /// Constructor
                 IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
                                 MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM)
                 {
+                    //If Bit 15 is 1 then Sign Extend
+                    int32_t temp = imm & 0x00008000;
+
+                    if (temp > 0 && mnemonic != "lui") {
+                        imm |= 0xFFFF0000;
+                    }
                 }
 
                 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+
+
         };
 
 }};
@@ -43,15 +54,59 @@ output header {{
 output decoder {{
         std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
         {
-                return "Disassembly of integer instruction\n";
+            std::stringstream ss;
+
+            ccprintf(ss, "%-10s ", mnemonic);
+
+            // just print the first dest... if there's a second one,
+            // it's generally implicit
+            if (_numDestRegs > 0) {
+                printReg(ss, _destRegIdx[0]);
+            }
+
+            ss << ",";
+
+            // just print the first two source regs... if there's
+            // a third one, it's a read-modify-write dest (Rc),
+            // e.g. for CMOVxx
+            if (_numSrcRegs > 0) {
+                printReg(ss, _srcRegIdx[0]);
+            }
+
+            if (_numSrcRegs > 1) {
+                ss << ",";
+                printReg(ss, _srcRegIdx[1]);
+            }
+
+            return ss.str();
         }
 
         std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
         {
-                return "Disassembly of integer immediate instruction\n";
+            std::stringstream ss;
+
+            ccprintf(ss, "%-10s ", mnemonic);
+
+            if (_numDestRegs > 0) {
+                printReg(ss, _destRegIdx[0]);
+            }
+
+            ss << ",";
+
+            if (_numSrcRegs > 0) {
+                printReg(ss, _srcRegIdx[0]);
+                ss << ",";
+            }
+
+            if( mnemonic == "lui")
+                ccprintf(ss, "%08p ", imm);
+            else
+                ss << (int) imm;
+
+            return ss.str();
         }
-}};
 
+}};
 
 //Used by decoder.isa
 def format IntOp(code, *opt_flags) {{
diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa
index fcdb577c6..8a07e63d4 100644
--- a/arch/mips/isa/formats/mem.isa
+++ b/arch/mips/isa/formats/mem.isa
@@ -40,6 +40,7 @@ output header {{
         const StaticInstPtr eaCompPtr;
         /// Pointer to MemAcc object.
         const StaticInstPtr memAccPtr;
+
         /// Displacement for EA calculation (signed).
         int32_t disp;
 
@@ -51,6 +52,12 @@ output header {{
               memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr),
               disp(OFFSET)
         {
+            //If Bit 15 is 1 then Sign Extend
+            int32_t temp = disp & 0x00008000;
+
+            if (temp > 0) {
+                disp |= 0xFFFF0000;
+            }
         }
 
         std::string
@@ -70,7 +77,7 @@ output decoder {{
     Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     {
         return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
-                        flags[IsFloating] ? 'f' : 'r', RS, JMPTARG, RT);
+                        flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
     }
 
 }};
diff --git a/arch/mips/isa/formats/noop.isa b/arch/mips/isa/formats/noop.isa
index 05c5ac10f..d35179005 100644
--- a/arch/mips/isa/formats/noop.isa
+++ b/arch/mips/isa/formats/noop.isa
@@ -59,7 +59,7 @@ output exec {{
     Fault
     Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
     {
-        return No_Fault;
+        return NoFault;
     }
 }};
 
@@ -68,9 +68,11 @@ output exec {{
 def template OperateNopCheckDecode {{
  {
      MipsStaticInst *i = new %(class_name)s(machInst);
-     if (RD == 0) {
-         i = makeNop(i);
-     }
+
+     //if (RD == 0) {
+     //  i = makeNop(i);
+     //}
+
      return i;
  }
 }};
diff --git a/arch/mips/isa/formats/trap.isa b/arch/mips/isa/formats/trap.isa
index 78f8d87b0..6884d4fa8 100644
--- a/arch/mips/isa/formats/trap.isa
+++ b/arch/mips/isa/formats/trap.isa
@@ -42,12 +42,11 @@ def template TrapExecute {{
 }};
 
 // Primary format for integer operate instructions:
-def format Trap(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+def format Trap(code, *flags) {{
+        code = 'bool cond;\n' + code;
+        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = TrapExecute.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
 }};
diff --git a/arch/mips/isa/formats/unimp.isa b/arch/mips/isa/formats/unimp.isa
index a7a71c681..adbd5b5b1 100644
--- a/arch/mips/isa/formats/unimp.isa
+++ b/arch/mips/isa/formats/unimp.isa
@@ -111,7 +111,7 @@ output exec {{
     {
         panic("attempt to execute unimplemented instruction '%s' "
               "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
-        return Unimplemented_Opcode_Fault;
+        return UnimplementedOpcodeFault;
     }
 
     Fault
@@ -123,7 +123,7 @@ output exec {{
             warned = true;
         }
 
-        return No_Fault;
+        return NoFault;
     }
 }};
 
diff --git a/arch/mips/isa/formats/unknown.isa b/arch/mips/isa/formats/unknown.isa
index 6eba5b4f9..4601b3684 100644
--- a/arch/mips/isa/formats/unknown.isa
+++ b/arch/mips/isa/formats/unknown.isa
@@ -42,7 +42,7 @@ output exec {{
     {
         panic("attempt to execute unknown instruction "
               "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
-        return Unimplemented_Opcode_Fault;
+        return UnimplementedOpcodeFault;
     }
 }};
 
diff --git a/arch/mips/isa/formats/util.isa b/arch/mips/isa/formats/util.isa
index c06877b35..db4bf204a 100644
--- a/arch/mips/isa/formats/util.isa
+++ b/arch/mips/isa/formats/util.isa
@@ -1,29 +1,6 @@
 // -*- mode:c++ -*-
 
 let {{
-def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
-    # Declare basic control transfer w/o link (i.e. link reg is R31)
-    nolink_code = 'NPC = %s;\n' % npc_expr
-    nolink_iop = InstObjParams(name, Name, base_class,
-                               CodeBlock(nolink_code), flags)
-    header_output = BasicDeclare.subst(nolink_iop)
-    decoder_output = BasicConstructor.subst(nolink_iop)
-    exec_output = BasicExecute.subst(nolink_iop)
-
-    # Generate declaration of '*AndLink' version, append to decls
-    link_code = 'Ra = NPC & ~3;\n' + nolink_code
-    link_iop = InstObjParams(name, Name + 'AndLink', base_class,
-                             CodeBlock(link_code), flags)
-    header_output += BasicDeclare.subst(link_iop)
-    decoder_output += BasicConstructor.subst(link_iop)
-    exec_output += BasicExecute.subst(link_iop)
-
-    # need to use link_iop for the decode template since it is expecting
-    # the shorter version of class_name (w/o "AndLink")
-
-    return (header_output, decoder_output,
-            JumpOrBranchDecode.subst(nolink_iop), exec_output)
-
 def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
                   postacc_code = '', base_class = 'Memory',
                   decode_template = BasicDecode, exec_template_base = ''):
@@ -116,10 +93,56 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
 
 output exec {{
 
+using namespace MipsISA;
+
+
     /// CLEAR ALL CPU INST/EXE HAZARDS
     inline void
     clear_exe_inst_hazards()
     {
         //CODE HERE
     }
+
+
+    /// Check "FP enabled" machine status bit.  Called when executing any FP
+    /// instruction in full-system mode.
+    /// @retval Full-system mode: NoFault if FP is enabled, FenFault
+    /// if not.  Non-full-system mode: always returns NoFault.
+#if FULL_SYSTEM
+    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
+    {
+        Fault fault = NoFault;	// dummy... this ipr access should not fault
+        if (!Mips34k::ICSR_FPE(xc->readIpr(MipsISA::IPR_ICSR, fault))) {
+            fault = FloatEnableFault;
+        }
+        return fault;
+    }
+#else
+    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
+    {
+        return NoFault;
+    }
+#endif
+
+    double convert_and_round(float w, int x, int y, int z)
+    {
+        double temp = .34000;
+
+        return temp;
+    }
+
+    enum FPTypes{
+        FP_SINGLE,
+        FP_DOUBLE,
+        FP_LONG,
+        FP_PS_LO,
+        FP_PS_HI,
+        FP_WORD,
+        RND_NEAREST,
+        RND_ZERO,
+        RND_UP,
+        RND_DOWN
+    };
 }};
+
+