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authorKorey Sewell <ksewell@umich.edu>2006-03-08 02:05:38 -0500
committerKorey Sewell <ksewell@umich.edu>2006-03-08 02:05:38 -0500
commit20e9a90edcaae9c91280abce0340b602ce4d313e (patch)
treef651ed84264cb75ab02d9b368f9a67c75c4a2905 /arch/mips/isa/operands.isa
parentab67095b2a43b5f2d44d1e1a517d1079ddf9f104 (diff)
downloadgem5-20e9a90edcaae9c91280abce0340b602ce4d313e.tar.xz
updated MIPS ISA files .... all files should be able to compile/build with MIPS option except isa_traits.*
which I need to update the misc. regfile accesses arch/mips/faults.cc: arch/mips/faults.hh: alpha to mips arch/mips/isa/base.isa: add includes arch/mips/isa/bitfields.isa: more bitfields arch/mips/isa/decoder.isa: lots o' lots o' lots o' changes!!!! arch/mips/isa/formats.isa: include cop0.isa arch/mips/isa/formats/basic.isa: fix faults arch/mips/isa/formats/branch.isa: arch/mips/isa/formats/fp.isa: arch/mips/isa/formats/int.isa: arch/mips/isa/formats/mem.isa: arch/mips/isa/formats/noop.isa: arch/mips/isa/formats/trap.isa: arch/mips/isa/formats/unimp.isa: arch/mips/isa/formats/unknown.isa: arch/mips/isa/formats/util.isa: arch/mips/isa/operands.isa: arch/mips/isa_traits.cc: arch/mips/linux_process.cc: merge MIPS-specific comilable/buidable files code into multiarch arch/mips/isa_traits.hh: merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have need to be recoded and everything should build then ... arch/mips/stacktrace.hh: file copied over --HG-- extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f
Diffstat (limited to 'arch/mips/isa/operands.isa')
-rw-r--r--arch/mips/isa/operands.isa11
1 files changed, 4 insertions, 7 deletions
diff --git a/arch/mips/isa/operands.isa b/arch/mips/isa/operands.isa
index 65ef2245f..13870337b 100644
--- a/arch/mips/isa/operands.isa
+++ b/arch/mips/isa/operands.isa
@@ -16,21 +16,18 @@ def operands {{
'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
- 'R31': ('IntReg', 'uw','R31','IsInteger', 4),
+ 'r31': ('IntReg', 'uw','R31','IsInteger', 4),
+ 'R0': ('IntReg', 'uw','R0', 'IsInteger', 5),
'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
- 'Sa': ('IntReg', 'uw', 'SA', 'IsInteger', 4),
'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
+ 'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
- 'NNPC': ('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
- #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
- #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
- # The next two are hacks for non-full-system call-pal emulation
- #'R0': ('IntReg', 'uq', '0', None, 1),
+ 'NNPC':('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
}};