Merge ktlim@zizzer:/bk/m5

into  zamp.eecs.umich.edu:/z/ktlim2/m5-proxyxc

arch/alpha/ev5.cc:
cpu/o3/cpu.hh:
    SCCS merged

--HG--
extra : convert_revision : 38889011ea02005c8fd3a7f3b0be3395223f6166

1 files changed, 4 insertions, 7 deletions

diff --git a/arch/mips/isa/operands.isa b/arch/mips/isa/operands.isa
index 65ef2245f..13870337b 100644
--- a/arch/mips/isa/operands.isa
+++ b/arch/mips/isa/operands.isa
@@ -16,21 +16,18 @@ def operands {{
     'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
     'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
     'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
-    'R31': ('IntReg', 'uw','R31','IsInteger', 4),
+    'r31': ('IntReg', 'uw','R31','IsInteger', 4),
+    'R0':  ('IntReg', 'uw','R0', 'IsInteger', 5),
 
     'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
-    'Sa': ('IntReg', 'uw', 'SA', 'IsInteger', 4),
 
     'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
     'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
     'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
+    'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
 
     'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
 
     'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
-    'NNPC': ('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
-    #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
-    #'FPCR':  ('ControlReg', 'uq', 'Fpcr', None, 1),
-    # The next two are hacks for non-full-system call-pal emulation
-    #'R0':  ('IntReg', 'uq', '0', None, 1),
+    'NNPC':('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
 }};