Support NNPC and branch instructions ... Outputs to decoder.cc correctly

Edits to the CPU model may still need to be made to handle branch likely insts...

arch/isa_parser.py:
    add a NNPC operand ...
arch/mips/isa/base.isa:
    change SPARC to MIPS
arch/mips/isa/decoder.isa:
    typo < to >=
arch/mips/isa/formats/basic.isa:
    spacing
arch/mips/isa/formats/branch.isa:
    add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
    support for NNPC and R31
arch/mips/isa_traits.hh:
    NNPC Addr variable

--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad

1 files changed, 4 insertions, 3 deletions

diff --git a/arch/mips/isa/operands.isa b/arch/mips/isa/operands.isa
index 19d21ac8d..77035f04c 100644
--- a/arch/mips/isa/operands.isa
+++ b/arch/mips/isa/operands.isa
@@ -16,6 +16,7 @@ def operands {{
     'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
     'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
     'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
+    'R31': ('IntReg', 'uw','R31','IsInteger', 4),
 
     'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
     'Sa': ('IntReg', 'uw', 'SA', 'IsInteger', 4),
@@ -24,12 +25,12 @@ def operands {{
     'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
     'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
 
-    'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4)
+    'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
 
-    #'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
+    'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
+    'NNPC': ('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
     #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
     #'FPCR':  ('ControlReg', 'uq', 'Fpcr', None, 1),
     # The next two are hacks for non-full-system call-pal emulation
     #'R0':  ('IntReg', 'uq', '0', None, 1),
-    #'R31': ('IntReg', 'uw', '31', None, 1)
 }};