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authorKorey Sewell <ksewell@umich.edu>2006-02-18 04:17:11 -0500
committerKorey Sewell <ksewell@umich.edu>2006-02-18 04:17:11 -0500
commit159e3345314b921f05f808ace06d62adf79f095a (patch)
treea3ab5941b3f1497c70b90bd2009747fa02ab4eb6 /arch/mips/isa/operands.isa
parent6bf71f96f3ae17e49eca8b77bf1f99b2883f93f6 (diff)
downloadgem5-159e3345314b921f05f808ace06d62adf79f095a.tar.xz
use string name to figure out if we have a "AndLink" instruction
arch/mips/isa/operands.isa: uq -> uw --HG-- extra : convert_revision : eeac6dba813de8174d080a5fa9b5a396b345113a
Diffstat (limited to 'arch/mips/isa/operands.isa')
-rw-r--r--arch/mips/isa/operands.isa4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/isa/operands.isa b/arch/mips/isa/operands.isa
index cf6f10e0b..19d21ac8d 100644
--- a/arch/mips/isa/operands.isa
+++ b/arch/mips/isa/operands.isa
@@ -26,10 +26,10 @@ def operands {{
'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4)
- #'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
+ #'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
# The next two are hacks for non-full-system call-pal emulation
#'R0': ('IntReg', 'uq', '0', None, 1),
- #'R16': ('IntReg', 'uq', '16', None, 1)
+ #'R31': ('IntReg', 'uw', '31', None, 1)
}};