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| author | Korey Sewell <ksewell@umich.edu> | 2006-02-20 14:30:23 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2006-02-20 14:30:23 -0500 |
| commit | 19534176e06578cb167d5f10d9146f6b1c361cb5 (patch) | |
| tree | c9bbff469d8d5a05b933aa98c2ed038a1e4e848c /arch/mips/isa/operands.isa | |
| parent | 38ce95db3b7cf471dcd3c12b784877c4dc238d6f (diff) | |
| download | gem5-19534176e06578cb167d5f10d9146f6b1c361cb5.tar.xz | |
load/store instruction format ... now generates load/store code
and breaks it into a separate EA and MemAccess templated
from how the Alpha ARch. was coded to do the same thing.
arch/mips/isa/bitfields.isa:
comment change
arch/mips/isa/decoder.isa:
re-structuring of load/store instruction definitions
arch/mips/isa/formats/mem.isa:
Define LoadMemory & Store Memory formats
Use style of formatting & base class similar to what was used for ALPHA
arch/mips/isa/formats/util.isa:
Insert LoadStoreBase function here from alpha/arch/isa/mem.isa
arch/mips/isa/operands.isa:
change shw->sh and uhw->uh
--HG--
extra : convert_revision : 5d85f15f4a600dd4c473a3b4a170ba39cf07fc8a
Diffstat (limited to 'arch/mips/isa/operands.isa')
| -rw-r--r-- | arch/mips/isa/operands.isa | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/isa/operands.isa b/arch/mips/isa/operands.isa index 77035f04c..65ef2245f 100644 --- a/arch/mips/isa/operands.isa +++ b/arch/mips/isa/operands.isa @@ -1,8 +1,8 @@ def operand_types {{ 'sb' : ('signed int', 8), 'ub' : ('unsigned int', 8), - 'shw' : ('signed int', 16), - 'uhw' : ('unsigned int', 16), + 'sh' : ('signed int', 16), + 'uh' : ('unsigned int', 16), 'sw' : ('signed int', 32), 'uw' : ('unsigned int', 32), 'sd' : ('signed int', 64), |