Polishing of isa_parser.py internal operand handling, resulting in

minor change to syntax of 'def operands' in ISA descriptions.

arch/alpha/isa/main.isa:
arch/mips/isa/operands.isa:
arch/sparc/isa/operands.isa:
    Change 'def operands' statement to work with new
    isa_parser changes.
arch/isa_parser.py:
    Merge OperandTraits and OperandDescriptor objects into a
    unified hierarchy of Operand objects.
    Required a change in the syntax of the 'def operands'
    statement in the ISA description.

--HG--
extra : convert_revision : cb43f1607311497ead88ba13953d410ab5bc6a37

1 files changed, 14 insertions, 15 deletions

diff --git a/arch/mips/isa/operands.isa b/arch/mips/isa/operands.isa
index 58fa2d3cf..c8e08a436 100644
--- a/arch/mips/isa/operands.isa
+++ b/arch/mips/isa/operands.isa
@@ -13,24 +13,23 @@ def operand_types {{
 }};
 
 def operands {{
-    'Rd': IntRegOperandTraits('uw', 'RD', 'IsInteger', 1),
-    'Rs': IntRegOperandTraits('uw', 'RS', 'IsInteger', 2),
-    'Rt': IntRegOperandTraits('uw', 'RT', 'IsInteger', 3),
+    'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
+    'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
+    'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
 
-    'IntImm': IntRegOperandTraits('uw', 'INTIMM', 'IsInteger', 3),
-    'Sa': IntRegOperandTraits('uw', 'SA', 'IsInteger', 4),
+    'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
+    'Sa': ('IntReg', 'uw', 'SA', 'IsInteger', 4),
 
-    'Fd': FloatRegOperandTraits('sf', 'FD', 'IsFloating', 1),
-    'Fs': FloatRegOperandTraits('sf', 'FS', 'IsFloating', 2),
-    'Ft': FloatRegOperandTraits('sf', 'FT', 'IsFloating', 3),
+    'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
+    'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
+    'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
 
-    'Mem': MemOperandTraits('udw', None,
-                            ('IsMemRef', 'IsLoad', 'IsStore'), 4)
+    'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4)
 
-    #'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
-    #'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
-    #'FPCR':  ControlRegOperandTraits('uq', 'Fpcr', None, 1),
+    #'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
+    #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
+    #'FPCR':  ('ControlReg', 'uq', 'Fpcr', None, 1),
     # The next two are hacks for non-full-system call-pal emulation
-    #'R0':  IntRegOperandTraits('uq', '0', None, 1),
-    #'R16': IntRegOperandTraits('uq', '16', None, 1)
+    #'R0':  ('IntReg', 'uq', '0', None, 1),
+    #'R16': ('IntReg', 'uq', '16', None, 1)
 }};