Hand merge. Stuff probably doesn't compile.

--HG--
rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux/process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux/process.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64/process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64/process.hh
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : 7d1efcedd708815d985a951f6f010fbd83dc27e8

18 files changed, 2848 insertions, 0 deletions

diff --git a/arch/mips/isa/base.isa b/arch/mips/isa/base.isa
new file mode 100644
index 000000000..4125b5101
--- /dev/null
+++ b/arch/mips/isa/base.isa
@@ -0,0 +1,96 @@
+// -*- mode:c++ -*-
+
+////////////////////////////////////////////////////////////////////
+//
+// Base class for MIPS instructions, and some support functions
+//
+
+//Outputs to decoder.hh
+output header {{
+
+#define R31 31
+#include "arch/mips/faults.hh"
+#include "arch/mips/isa_traits.hh"
+
+    using namespace MipsISA;
+
+
+    /**
+     * Base class for all MIPS static instructions.
+     */
+    class MipsStaticInst : public StaticInst
+    {
+      protected:
+
+        /// Make MipsISA register dependence tags directly visible in
+        /// this class and derived classes.  Maybe these should really
+        /// live here and not in the MipsISA namespace.
+        /*enum DependenceTags {
+            FP_Base_DepTag = MipsISA::FP_Base_DepTag,
+            Fpcr_DepTag = MipsISA::Fpcr_DepTag,
+            Uniq_DepTag = MipsISA::Uniq_DepTag,
+            IPR_Base_DepTag = MipsISA::IPR_Base_DepTag
+            };*/
+
+        // Constructor
+        MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
+            : StaticInst(mnem, _machInst, __opClass)
+        {
+        }
+
+        /// Print a register name for disassembly given the unique
+        /// dependence tag number (FP or int).
+        void printReg(std::ostream &os, int reg) const;
+
+        std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+
+}};
+
+//Ouputs to decoder.cc
+output decoder {{
+
+    void MipsStaticInst::printReg(std::ostream &os, int reg) const
+    {
+        if (reg < FP_Base_DepTag) {
+            ccprintf(os, "r%d", reg);
+        }
+        else {
+            ccprintf(os, "f%d", reg - FP_Base_DepTag);
+        }
+    }
+
+    std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        std::stringstream ss;
+
+        ccprintf(ss, "%-10s ", mnemonic);
+
+        // just print the first two source regs... if there's
+        // a third one, it's a read-modify-write dest (Rc),
+        // e.g. for CMOVxx
+        if(_numSrcRegs > 0)
+        {
+            printReg(ss, _srcRegIdx[0]);
+        }
+
+        if(_numSrcRegs > 1)
+        {
+            ss << ",";
+            printReg(ss, _srcRegIdx[1]);
+        }
+
+        // just print the first dest... if there's a second one,
+        // it's generally implicit
+        if(_numDestRegs > 0)
+        {
+            if(_numSrcRegs > 0)
+                ss << ",";
+            printReg(ss, _destRegIdx[0]);
+        }
+
+        return ss.str();
+    }
+
+}};
+
diff --git a/arch/mips/isa/bitfields.isa b/arch/mips/isa/bitfields.isa
new file mode 100644
index 000000000..58d487ad2
--- /dev/null
+++ b/arch/mips/isa/bitfields.isa
@@ -0,0 +1,67 @@
+// -*- mode:c++ -*-
+
+////////////////////////////////////////////////////////////////////
+//
+// Bitfield definitions.
+//
+
+def bitfield OPCODE     <31:26>;
+def bitfield OPCODE_HI  <31:29>;
+def bitfield OPCODE_LO  <28:26>;
+
+def bitfield REGIMM      <20:16>;
+def bitfield REGIMM_HI   <20:19>;
+def bitfield REGIMM_LO   <18:16>;
+
+def bitfield FUNCTION      < 5: 0>;
+def bitfield FUNCTION_HI   < 5: 3>;
+def bitfield FUNCTION_LO   < 2: 0>;
+
+// Integer operate format
+def bitfield RT	      <20:16>;
+def bitfield RT_HI    <20:19>;
+def bitfield RT_LO    <18:16>;
+
+def bitfield RS	      <25:21>;
+def bitfield RS_MSB   <25:25>;
+def bitfield RS_HI    <25:24>;
+def bitfield RS_LO    <23:21>;
+
+def bitfield RD	      <15:11>;
+
+def bitfield INTIMM	<15: 0>; // integer immediate (literal)
+
+// Floating-point operate format
+def bitfield FMT      <25:21>;
+def bitfield FR       <25:21>;
+def bitfield FT	      <20:16>;
+def bitfield FS	      <15:11>;
+def bitfield FD	      <10:6>;
+
+def bitfield CC       <20:18>;
+def bitfield ND       <17:17>;
+def bitfield TF       <16:16>;
+def bitfield MOVCI    <16:16>;
+def bitfield MOVCF    <16:16>;
+def bitfield SRL      <21:21>;
+def bitfield SRLV     < 6: 6>;
+def bitfield SA       <10: 6>;
+
+// CP0 Register Select
+def bitfield SEL       < 2: 0>;
+
+// Interrupts
+def bitfield SC       < 5: 5>;
+
+// Branch format
+def bitfield OFFSET <15: 0>; // displacement
+
+// Jmp format
+def bitfield JMPTARG	<25: 0>;
+def bitfield HINT	<10: 6>;
+
+def bitfield SYSCALLCODE <25: 6>;
+def bitfield TRAPCODE    <15:13>;
+
+// M5 instructions
+def bitfield M5FUNC <7:0>;
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
new file mode 100644
index 000000000..3f054f6a5
--- /dev/null
+++ b/arch/mips/isa/decoder.isa
@@ -0,0 +1,930 @@
+// -*- mode:c++ -*-
+
+////////////////////////////////////////////////////////////////////
+//
+// The actual MIPS32 ISA decoder
+// -----------------------------
+// The following instructions are specified in the MIPS32 ISA
+// Specification. Decoding closely follows the style specified
+// in the MIPS32 ISAthe specification document starting with Table
+// A-2 (document available @ www.mips.com)
+//
+//@todo: Distinguish "unknown/future" use insts from "reserved"
+// ones
+decode OPCODE_HI default Unknown::unknown() {
+
+    // Derived From ... Table A-2 MIPS32 ISA Manual
+    0x0: decode OPCODE_LO {
+
+        0x0: decode FUNCTION_HI {
+            0x0: decode FUNCTION_LO {
+                0x1: decode MOVCI {
+                    format BasicOp {
+                        0: movf({{ if (xc->readMiscReg(FPCR,0) != CC) Rd = Rs}});
+                        1: movt({{ if (xc->readMiscReg(FPCR,0) == CC) Rd = Rs}});
+                    }
+                }
+
+                format BasicOp {
+
+                    //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields
+                    //are used to distinguish among the SLL, NOP, SSNOP and EHB functions."
+
+                    0x0: decode RS {
+                        0x0: decode RT default BasicOp::sll({{ Rd = Rt.uw << SA; }}) {
+                            0x0: decode RD{
+                                0x0: decode HINT {
+                                    0x0:nop({{}});  //really sll r0,r0,0
+                                    0x1:ssnop({{}});//really sll r0,r0,1
+                                    0x3:ehb({{}});  //really sll r0,r0,3
+                                }
+                            }
+                        }
+                    }
+
+                    0x2: decode SRL {
+                        0: srl({{ Rd = Rt.uw >> SA; }});
+
+                        //Hardcoded assuming 32-bit ISA, probably need parameter here
+                        1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
+                    }
+
+                    0x3: sra({{ Rd = Rt.sw >> SA; }});
+
+                    0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
+
+                    0x6: decode SRLV {
+                        0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});
+
+                        //Hardcoded assuming 32-bit ISA, probably need parameter here
+                        1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
+                    }
+
+                    0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }});
+                }
+            }
+
+            0x1: decode FUNCTION_LO {
+
+                //Table A-3 Note: "Specific encodings of the hint field are used
+                //to distinguish JR from JR.HB and JALR from JALR.HB"
+                format Jump {
+                    0x0: decode HINT {
+                        0:jr({{ NNPC = Rs & ~1; }},IsReturn);
+
+                        1:jr_hb({{ NNPC = Rs & ~1; clear_exe_inst_hazards(); }},IsReturn);
+                    }
+
+                    0x1: decode HINT {
+                        0: jalr({{ NNPC = Rs; }},IsCall,IsReturn);
+
+                        1: jalr_hb({{ NNPC = Rs; clear_exe_inst_hazards();}},IsCall,IsReturn);
+                    }
+                }
+
+                format BasicOp {
+                    0x2: movz({{ if (Rt == 0) Rd = Rs; }});
+                    0x3: movn({{ if (Rt != 0) Rd = Rs; }});
+                }
+
+                format WarnUnimpl {
+                    0x4: syscall();//{{ xc->syscall()}},IsNonSpeculative
+                    0x5: break();
+                    0x7: sync();
+                }
+            }
+
+            0x2: decode FUNCTION_LO {
+                format BasicOp {
+                    0x0: mfhi({{ Rd = xc->readMiscReg(Hi); }});
+                    0x1: mthi({{ xc->setMiscReg(Hi,Rs); }});
+                    0x2: mflo({{ Rd = xc->readMiscReg(Lo); }});
+                    0x3: mtlo({{ xc->setMiscReg(Lo,Rs); }});
+                }
+            }
+
+            0x3: decode FUNCTION_LO {
+                format IntOp {
+                    0x0: mult({{
+                        int64_t temp1 = Rs.sw * Rt.sw;
+                        xc->setMiscReg(Hi,temp1<63:32>);
+                        xc->setMiscReg(Lo,temp1<31:0>);
+                    }});
+
+                    0x1: multu({{
+                        int64_t temp1 = Rs.uw * Rt.uw;
+                        xc->setMiscReg(Hi,temp1<63:32>);
+                        xc->setMiscReg(Lo,temp1<31:0>);
+                    }});
+
+                    0x2: div({{
+                        xc->setMiscReg(Hi,Rs.sw % Rt.sw);
+                        xc->setMiscReg(Lo,Rs.sw / Rt.sw);
+                    }});
+
+                    0x3: divu({{
+                        xc->setMiscReg(Hi,Rs.uw % Rt.uw);
+                        xc->setMiscReg(Lo,Rs.uw / Rt.uw);
+                    }});
+                }
+            }
+
+            0x4: decode FUNCTION_LO {
+                format IntOp {
+                    0x0: add({{  Rd.sw = Rs.sw + Rt.sw;/*Trap on Overflow*/}});
+                    0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
+                    0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}});
+                    0x3: subu({{ Rd.sw = Rs.sw - Rt.uw;}});
+                    0x4: and({{ Rd = Rs & Rt;}});
+                    0x5: or({{ Rd = Rs | Rt;}});
+                    0x6: xor({{ Rd = Rs ^ Rt;}});
+                    0x7: nor({{ Rd = ~(Rs | Rt);}});
+                }
+            }
+
+            0x5: decode FUNCTION_LO {
+                format IntOp{
+                    0x2: slt({{  Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
+                    0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
+                }
+            }
+
+            0x6: decode FUNCTION_LO {
+                format Trap {
+                    0x0: tge({{  cond = (Rs.sw >= Rt.sw); }});
+                    0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
+                    0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
+                    0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
+                    0x4: teq({{ cond = (Rs.sw == Rt.sw); }});
+                    0x6: tne({{ cond = (Rs.sw != Rt.sw); }});
+                }
+            }
+        }
+
+        0x1: decode REGIMM_HI {
+            0x0: decode REGIMM_LO {
+                format Branch {
+                    0x0: bltz({{ cond = (Rs.sw < 0); }});
+                    0x1: bgez({{ cond = (Rs.sw >= 0); }});
+                }
+
+                format BranchLikely {
+                    //MIPS obsolete instructions
+                    0x2: bltzl({{ cond = (Rs.sw < 0); }});
+                    0x3: bgezl({{ cond = (Rs.sw >= 0); }});
+                }
+            }
+
+            0x1: decode REGIMM_LO {
+                format Trap {
+                    0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
+                    0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
+                    0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
+                    0x3: tltiu({{ cond = (Rs.uw < INTIMM); }});
+                    0x4: teqi( {{ cond = (Rs.sw == INTIMM);}});
+                    0x6: tnei( {{ cond = (Rs.sw != INTIMM);}});
+                }
+            }
+
+            0x2: decode REGIMM_LO {
+                format Branch {
+                    0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsCall,IsReturn);
+                    0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsCall,IsReturn);
+                }
+
+                format BranchLikely {
+                    //Will be removed in future MIPS releases
+                    0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsCall, IsReturn);
+                    0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsCall, IsReturn);
+                }
+            }
+
+            0x3: decode REGIMM_LO {
+                format WarnUnimpl {
+                    0x7: synci();
+                }
+            }
+        }
+
+        format Jump {
+            0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}});
+
+            0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},IsCall,IsReturn);
+        }
+
+        format Branch {
+            0x4: beq({{ cond = (Rs.sw == Rt.sw); }});
+            0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
+            0x6: blez({{ cond = (Rs.sw <= 0); }});
+            0x7: bgtz({{ cond = (Rs.sw > 0); }});
+        }
+    }
+
+    0x1: decode OPCODE_LO {
+        format IntOp {
+            0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
+            0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
+            0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
+            0x3: sltiu({{ Rt.sw = ( Rs.sw < imm ) ? 1 : 0 }});
+            0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}});
+            0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}});
+            0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}});
+            0x7: lui({{ Rt = INTIMM << 16}});
+        }
+    }
+
+    0x2: decode OPCODE_LO {
+
+        //Table A-11 MIPS32 COP0 Encoding of rs Field
+        0x0: decode RS_MSB {
+            0x0: decode RS {
+                format System {
+                    0x0: mfc0({{
+                        //uint64_t reg_num = Rd.uw;
+
+                        Rt = xc->readMiscReg(RD << 5 | SEL);
+                    }});
+
+                    0x4: mtc0({{
+                        //uint64_t reg_num = Rd.uw;
+
+                        xc->setMiscReg(RD << 5 | SEL,Rt);
+                    }});
+
+                    0x8: mftr({{
+                        //The contents of the coprocessor 0 register specified by the
+                        //combination of rd and sel are loaded into general register
+                        //rt. Note that not all coprocessor 0 registers support the
+                        //sel field. In those instances, the sel field must be zero.
+
+                        //MT Code Needed Here
+                    }});
+
+                    0xC: mttr({{
+                        //The contents of the coprocessor 0 register specified by the
+                        //combination of rd and sel are loaded into general register
+                        //rt. Note that not all coprocessor 0 registers support the
+                        //sel field. In those instances, the sel field must be zero.
+
+                        //MT Code Needed Here
+                    }});
+
+
+                    0xA: rdpgpr({{
+                        //Accessing Previous Shadow Set Register Number
+                        //uint64_t prev = xc->readMiscReg(SRSCtl)/*[PSS]*/;
+                        //uint64_t reg_num = Rt.uw;
+
+                        //Rd = xc->regs.IntRegFile[prev];
+                       //Rd = xc->shadowIntRegFile[prev][reg_num];
+                    }});
+
+                    0xB: decode RD {
+
+                        0x0: decode SC {
+                            0x0: dvpe({{
+                                int idx;
+                                int sel;
+                                getMiscRegIdx(MVPControl,idx,sel);
+                                Rt.sw = xc->readMiscReg(idx,sel);
+                                xc->setMiscReg(idx,sel);
+                            }});
+
+                            0x1: evpe({{
+                                int idx;
+                                int sel;
+                                getMiscRegIdx(MVPControl,idx,sel);
+                                Rt.sw = xc->readMiscReg(idx,sel);
+                                xc->setMiscReg(idx,sel,1);
+                            }});
+                        }
+
+                        0x1: decode SC {
+                            0x0: dmt({{
+                                int idx;
+                                int sel;
+                                getMiscRegIdx(VPEControl,idx,sel);
+                                Rt.sw = xc->readMiscReg(idx,sel);
+                                xc->setMiscReg(idx,sel);
+                            }});
+
+                            0x1: emt({{
+                                int idx;
+                                int sel;
+                                getMiscRegIdx(VPEControl,idx,sel);
+                                Rt.sw = xc->readMiscReg(idx,sel);
+                                xc->setMiscReg(idx,sel,1);
+                            }});
+                        }
+
+                        0xC: decode SC {
+                            0x0: di({{
+                                int idx;
+                                int sel;
+                                getMiscRegIdx(Status,idx,sel);
+                                Rt.sw = xc->readMiscReg(idx,sel);
+                                xc->setMiscReg(idx,sel);
+                            }});
+
+                            0x1: ei({{
+                                int idx;
+                                int sel;
+                                getMiscRegIdx(Status,idx,sel);
+                                Rt.sw = xc->readMiscReg(idx,sel);
+                                xc->setMiscReg(idx,sel,1);
+                            }});
+                        }
+                    }
+
+                    0xE: wrpgpr({{
+                        //Accessing Previous Shadow Set Register Number
+                        //uint64_t prev = xc->readMiscReg(SRSCtl/*[PSS]*/);
+                        //uint64_t reg_num = Rd.uw;
+
+                        //xc->regs.IntRegFile[prev];
+                        //xc->shadowIntRegFile[prev][reg_num] = Rt;
+                    }});
+                }
+            }
+
+            //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
+            0x1: decode FUNCTION {
+                format System {
+                    0x01: tlbr({{ }});
+                    0x02: tlbwi({{ }});
+                    0x06: tlbwr({{ }});
+                    0x08: tlbp({{ }});
+                }
+
+                format WarnUnimpl {
+                    0x18: eret();
+                    0x1F: deret();
+                    0x20: wait();
+                }
+            }
+        }
+
+        //Table A-13 MIPS32 COP1 Encoding of rs Field
+        0x1: decode RS_MSB {
+
+            0x0: decode RS_HI {
+                0x0: decode RS_LO {
+                    format FloatOp {
+                        0x0: mfc1({{ /*Rt.uw = Fs.ud<31:0>;*/ }});
+                        0x2: cfc1({{ /*Rt.uw = xc->readMiscReg(FPCR[Fs]);*/}});
+                        0x3: mfhc1({{ /*Rt.uw = Fs.ud<63:32>*/;}});
+                        0x4: mtc1({{ /*Fs = Rt.uw*/}});
+                        0x6: ctc1({{ /*xc->setMiscReg(FPCR[Fs],Rt);*/}});
+                        0x7: mthc1({{ /*Fs<63:32> = Rt.uw*/}});
+                    }
+                }
+
+                0x1: decode ND {
+                    0x0: decode TF {
+                        format Branch {
+                            0x0: bc1f({{ cond = (xc->readMiscReg(FPCR) == 0); }});
+                            0x1: bc1t({{ cond = (xc->readMiscReg(FPCR) == 1); }});
+                        }
+                    }
+
+                    0x1: decode TF {
+                        format BranchLikely {
+                            0x0: bc1fl({{ cond = (xc->readMiscReg(FPCR) == 0); }});
+                            0x1: bc1tl({{ cond = (xc->readMiscReg(FPCR) == 1); }});
+                        }
+                    }
+                }
+            }
+
+            0x1: decode RS_HI {
+                0x2: decode RS_LO {
+
+                    //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
+                    //(( single-word ))
+                    0x0: decode RS_HI {
+                        0x0: decode RS_LO {
+                            format FloatOp {
+                                0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}});
+                                0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}});
+                                0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}});
+                                0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}});
+                                0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}});
+                                0x5: abss({{ Fd.sf = fabs(Fs.sf);}});
+                                0x6: movs({{ Fd.sf = Fs.sf;}});
+                                0x7: negs({{ Fd.sf = -1 * Fs.sf;}});
+                            }
+                        }
+
+                        0x1: decode RS_LO {
+                            //only legal for 64 bit-FP
+                            format Float64Op {
+                                0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}});
+                                0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}});
+                                0x2: ceil_l_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_LONG,FP_SINGLE);}});
+                                0x3: floor_l_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_LONG,FP_SINGLE);}});
+                            }
+
+                            format FloatOp {
+                                0x4: round_w_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_WORD,FP_SINGLE);}});
+                                0x5: trunc_w_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_WORD,FP_SINGLE);}});
+                                0x6: ceil_w_s({{  Fd = convert_and_round(Fs.sf,RND_UP,FP_WORD,FP_SINGLE);}});
+                                0x7: floor_w_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_WORD,FP_SINGLE);}});
+                            }
+                        }
+
+                        0x2: decode RS_LO {
+                            0x1: decode MOVCF {
+                                format FloatOp {
+                                    0x0: movfs({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }});
+                                    0x1: movts({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}});
+                                }
+                            }
+
+                            format BasicOp {
+                                0x2: movzs({{ if (Rt == 0) Fd = Fs; }});
+                                0x3: movns({{ if (Rt != 0) Fd = Fs; }});
+                            }
+
+                            format Float64Op {
+                                0x5: recips({{ Fd = 1 / Fs; }});
+                                0x6: rsqrts({{ Fd = 1 / sqrt((double)Fs.ud);}});
+                            }
+                        }
+
+                        0x4: decode RS_LO {
+
+                            format FloatOp {
+                                0x1: cvt_d_s({{ int rnd_mode = xc->readMiscReg(FCSR);
+                                Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE);
+                                }});
+
+                                0x4: cvt_w_s({{ int rnd_mode = xc->readMiscReg(FCSR);
+                                Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE);
+                                }});
+                            }
+
+                            //only legal for 64 bit
+                            format Float64Op {
+                                0x5: cvt_l_s({{ int rnd_mode = xc->readMiscReg(FCSR);
+                                Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE);
+                                }});
+
+                                0x6: cvt_ps_s({{ /*Fd.df = Fs.df<31:0> | Ft.df<31:0>;*/ }});
+                            }
+                        }
+                    }
+
+                    //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D
+                    0x1: decode RS_HI {
+                        0x0: decode RS_LO {
+                            format FloatOp {
+                                0x0: addd({{ Fd.df = Fs.df + Ft.df;}});
+                                0x1: subd({{ Fd.df = Fs.df - Ft.df;}});
+                                0x2: muld({{ Fd.df = Fs.df * Ft.df;}});
+                                0x3: divd({{ Fd.df = Fs.df / Ft.df;}});
+                                0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}});
+                                0x5: absd({{ Fd.df = fabs(Fs.df);}});
+                                0x6: movd({{ Fd.df = Fs.df;}});
+                                0x7: negd({{ Fd.df = -1 * Fs.df;}});
+                            }
+                        }
+
+                        0x1: decode RS_LO {
+                            //only legal for 64 bit
+                            format Float64Op {
+                                0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }});
+                                0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}});
+                                0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}});
+                                0x3: floor_l_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE);}});
+                            }
+
+                            format FloatOp {
+                                0x4: round_w_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }});
+                                0x5: trunc_w_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE); }});
+                                0x6: ceil_w_d({{  Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE); }});
+                                0x7: floor_w_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE); }});
+                            }
+                        }
+
+                        0x2: decode RS_LO {
+                            0x1: decode MOVCF {
+                                format FloatOp {
+                                    0x0: movfd({{if (xc->readMiscReg(FPCR) != CC) Fd.df = Fs.df; }});
+                                    0x1: movtd({{if (xc->readMiscReg(FPCR) == CC) Fd.df = Fs.df; }});
+                                }
+                            }
+
+                            format BasicOp {
+                                0x2: movzd({{ if (Rt == 0) Fd.df = Fs.df; }});
+                                0x3: movnd({{ if (Rt != 0) Fd.df = Fs.df; }});
+                            }
+
+                            format Float64Op {
+                                0x5: recipd({{ Fd.df = 1 / Fs.df}});
+                                0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }});
+                            }
+                        }
+
+                        0x4: decode RS_LO {
+                            format FloatOp {
+                                0x0: cvt_s_d({{
+                                    int rnd_mode = xc->readMiscReg(FCSR);
+                                    Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE);
+                                }});
+
+                                0x4: cvt_w_d({{
+                                    int rnd_mode = xc->readMiscReg(FCSR);
+                                    Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE);
+                                }});
+                            }
+
+                            //only legal for 64 bit
+                            format Float64Op {
+                                0x5: cvt_l_d({{
+                                    int rnd_mode = xc->readMiscReg(FCSR);
+                                    Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE);
+                                }});
+                            }
+                        }
+                    }
+
+                    //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
+                    0x4: decode FUNCTION {
+                        format FloatOp {
+                            0x20: cvt_s({{
+                                int rnd_mode = xc->readMiscReg(FCSR);
+                                Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD);
+                            }});
+
+                            0x21: cvt_d({{
+                                int rnd_mode = xc->readMiscReg(FCSR);
+                                Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD);
+                            }});
+                        }
+                    }
+
+                    //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
+                    //Note: "1. Format type L is legal only if 64-bit floating point operations
+                    //are enabled."
+                    0x5: decode FUNCTION_HI {
+                        format FloatOp {
+                            0x10: cvt_s_l({{
+                                int rnd_mode = xc->readMiscReg(FCSR);
+                                Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG);
+                            }});
+
+                            0x11: cvt_d_l({{
+                                int rnd_mode = xc->readMiscReg(FCSR);
+                                Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG);
+                            }});
+                        }
+                    }
+
+                    //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
+                    //Note: "1. Format type PS is legal only if 64-bit floating point operations
+                    //are enabled. "
+                    0x6: decode RS_HI {
+                        0x0: decode RS_LO {
+                            format Float64Op {
+                                0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+                                    //Lower Halves Independently but we take simulator shortcut
+                                    Fd.df = Fs.df + Ft.df;
+                                }});
+
+                                0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+                                    //Lower Halves Independently but we take simulator shortcut
+                                    Fd.df = Fs.df - Ft.df;
+                                }});
+
+                                0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+                                    //Lower Halves Independently but we take simulator shortcut
+                                    Fd.df = Fs.df * Ft.df;
+                                }});
+
+                                0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+                                    //Lower Halves Independently but we take simulator shortcut
+                                    Fd.df = fabs(Fs.df);
+                                }});
+
+                                0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+                                    //Lower Halves Independently but we take simulator shortcut
+                                    //Fd.df = Fs<31:0> |  Ft<31:0>;
+                                }});
+
+                                0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+                                    //Lower Halves Independently but we take simulator shortcut
+                                    Fd.df = -1 * Fs.df;
+                                }});
+                            }
+                        }
+
+                        0x2: decode RS_LO {
+                            0x1: decode MOVCF {
+                                format Float64Op {
+                                    0x0: movfps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs;}});
+                                    0x1: movtps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}});
+                                }
+                            }
+
+                            format BasicOp {
+                                0x2: movzps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }});
+                                0x3: movnps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs; }});
+                            }
+
+                        }
+
+                        0x4: decode RS_LO {
+                            0x0: Float64Op::cvt_s_pu({{
+                                int rnd_mode = xc->readMiscReg(FCSR);
+                                Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI);
+                            }});
+                        }
+
+                        0x5: decode RS_LO {
+                            format Float64Op {
+                                0x0: cvt_s_pl({{
+                                    int rnd_mode = xc->readMiscReg(FCSR);
+                                    Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO);
+                                }});
+                                0x4: pll({{ /*Fd.df = Fs<31:0> | Ft<31:0>*/}});
+                                0x5: plu({{ /*Fd.df = Fs<31:0> | Ft<63:32>*/}});
+                                0x6: pul({{ /*Fd.df = Fs<63:32> | Ft<31:0>*/}});
+                                0x7: puu({{ /*Fd.df = Fs<63:32 | Ft<63:32>*/}});
+                            }
+                        }
+                    }
+                }
+            }
+        }
+
+        //Table A-19 MIPS32 COP2 Encoding of rs Field
+        0x2: decode RS_MSB {
+            0x0: decode RS_HI {
+                0x0: decode RS_LO {
+                    format WarnUnimpl {
+                        0x0: mfc2();
+                        0x2: cfc2();
+                        0x3: mfhc2();
+                        0x4: mtc2();
+                        0x6: ctc2();
+                        0x7: mftc2();
+                    }
+                }
+
+                0x1: decode ND {
+                    0x0: decode TF {
+                        format WarnUnimpl {
+                            0x0: bc2f();
+                            0x1: bc2t();
+                        }
+                    }
+
+                    0x1: decode TF {
+                        format WarnUnimpl {
+                            0x0: bc2fl();
+                            0x1: bc2tl();
+                        }
+                    }
+                }
+            }
+        }
+
+        //Table A-20 MIPS64 COP1X Encoding of Function Field 1
+        //Note: "COP1X instructions are legal only if 64-bit floating point
+        //operations are enabled."
+        0x3: decode FUNCTION_HI {
+            0x0: decode FUNCTION_LO {
+                format LoadMemory2 {
+                    0x0: lwxc1({{ EA = Rs + Rt; }},{{ /*F_t<31:0> = Mem.sf; */}});
+                    0x1: ldxc1({{ EA = Rs + Rt; }},{{ /*F_t<63:0> = Mem.df;*/ }});
+                    0x5: luxc1({{ //Need to make EA<2:0> = 0
+                        EA = Rs + Rt;
+                    }},
+                {{ /*F_t<31:0> = Mem.df; */}});
+                }
+            }
+
+            0x1: decode FUNCTION_LO {
+                format StoreMemory2 {
+                    0x0: swxc1({{ EA = Rs + Rt; }},{{ /*Mem.sf = Ft<31:0>; */}});
+                    0x1: sdxc1({{ EA = Rs + Rt; }},{{ /*Mem.df = Ft<63:0> */}});
+                    0x5: suxc1({{ //Need to make EA<2:0> = 0
+                        EA = Rs + Rt;
+                    }},
+                {{ /*Mem.df = F_t<63:0>;*/}});
+                }
+
+                0x7: WarnUnimpl::prefx();
+            }
+
+            format FloatOp {
+                0x3: WarnUnimpl::alnv_ps();
+
+                format BasicOp {
+                    0x4: decode FUNCTION_LO {
+                        0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }});
+                        0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }});
+                        0x6: madd_ps({{
+                            //Must Check for Exception Here... Supposed to Operate on Upper and
+                            //Lower Halves Independently but we take simulator shortcut
+                            Fd.df = (Fs.df * Fs.df) + Fr.df;
+                        }});
+                    }
+
+                    0x5: decode FUNCTION_LO {
+                        0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }});
+                        0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }});
+                        0x6: msub_ps({{
+                            //Must Check for Exception Here... Supposed to Operate on Upper and
+                            //Lower Halves Independently but we take simulator shortcut
+                            Fd.df = (Fs.df * Fs.df) - Fr.df;
+                        }});
+                    }
+
+                    0x6: decode FUNCTION_LO {
+                        0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }});
+                        0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }});
+                        0x6: nmadd_ps({{
+                            //Must Check for Exception Here... Supposed to Operate on Upper and
+                            //Lower Halves Independently but we take simulator shortcut
+                            Fd.df = (-1 * Fs.df * Fs.df) + Fr.df;
+                        }});
+                    }
+
+                    0x7: decode FUNCTION_LO {
+                        0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }});
+                        0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }});
+                        0x6: nmsub_ps({{
+                            //Must Check for Exception Here... Supposed to Operate on Upper and
+                            //Lower Halves Independently but we take simulator shortcut
+                            Fd.df = (-1 * Fs.df * Fs.df) + Fr.df;
+                        }});
+                    }
+                }
+            }
+        }
+
+        //MIPS obsolete instructions
+        format BranchLikely {
+            0x4: beql({{ cond = (Rs.sw == 0); }});
+            0x5: bnel({{ cond = (Rs.sw != 0); }});
+            0x6: blezl({{ cond = (Rs.sw <= 0); }});
+            0x7: bgtzl({{ cond = (Rs.sw > 0); }});
+        }
+    }
+
+    0x3: decode OPCODE_LO default FailUnimpl::reserved() {
+
+        //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
+        0x4: decode FUNCTION_HI {
+
+            0x0: decode FUNCTION_LO {
+                format IntOp {
+                    0x0: madd({{
+                        int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
+                        temp1 = temp1 + (Rs.sw * Rt.sw);
+                        xc->setMiscReg(Hi,temp1<63:32>);
+                        xc->setMiscReg(Lo,temp1<31:0>);
+                            }});
+
+                    0x1: maddu({{
+                        int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
+                        temp1 = temp1 + (Rs.uw * Rt.uw);
+                        xc->setMiscReg(Hi,temp1<63:32>);
+                        xc->setMiscReg(Lo,temp1<31:0>);
+                            }});
+
+                    0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; 	}});
+
+                    0x4: msub({{
+                        int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
+                        temp1 = temp1 - (Rs.sw * Rt.sw);
+                        xc->setMiscReg(Hi,temp1<63:32>);
+                        xc->setMiscReg(Lo,temp1<31:0>);
+                            }});
+
+                    0x5: msubu({{
+                        int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32;
+                        temp1 = temp1 - (Rs.uw * Rt.uw);
+                        xc->setMiscReg(Hi,temp1<63:32>);
+                        xc->setMiscReg(Lo,temp1<31:0>);
+                            }});
+                }
+            }
+
+            0x4: decode FUNCTION_LO {
+                format BasicOp {
+                    0x0: clz({{
+                        /*int cnt = 0;
+                        int idx = 0;
+                        while ( Rs.uw<idx> != 1) {
+                            cnt++;
+                            idx--;
+                        }
+
+                        Rd.uw = cnt;*/
+                    }});
+
+                    0x1: clo({{
+                        /*int cnt = 0;
+                        int idx = 0;
+                        while ( Rs.uw<idx> != 0) {
+                            cnt++;
+                            idx--;
+                        }
+
+                        Rd.uw = cnt;*/
+                    }});
+                }
+            }
+
+            0x7: decode FUNCTION_LO {
+                0x7: WarnUnimpl::sdbbp();
+            }
+        }
+
+        //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture
+        0x7: decode FUNCTION_HI {
+
+            0x0: decode FUNCTION_LO {
+                format WarnUnimpl {
+                    0x1: ext();
+                    0x4: ins();
+                }
+            }
+
+            0x1: decode FUNCTION_LO {
+                format WarnUnimpl {
+                    0x0: fork();
+                    0x1: yield();
+                }
+            }
+
+
+            //Table A-10 MIPS32 BSHFL Encoding of sa Field
+            0x4: decode SA {
+
+                0x02: WarnUnimpl::wsbh();
+
+                format BasicOp {
+                    0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24)  | */ Rt<7:0>}});
+                    0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}});
+                }
+            }
+
+            0x6: decode FUNCTION_LO {
+                0x7: BasicOp::rdhwr({{ /*Rt = xc->hwRegs[RD];*/ }});
+            }
+        }
+    }
+
+    0x4: decode OPCODE_LO default FailUnimpl::reserved() {
+        format LoadMemory {
+            0x0: lb({{ Rt.sw = Mem.sb; }});
+            0x1: lh({{ Rt.sw = Mem.sh; }});
+            0x2: lwl({{ Rt.sw = Mem.sw; }});//, WordAlign);
+            0x3: lw({{ Rt.sw = Mem.sb; }});
+            0x4: lbu({{ Rt.uw = Mem.ub; }});
+            0x5: lhu({{ Rt.uw = Mem.uh; }});
+            0x6: lwr({{ Rt.uw = Mem.uw; }});//, WordAlign);
+        }
+
+        0x7: FailUnimpl::reserved();
+    }
+
+    0x5: decode OPCODE_LO default FailUnimpl::reserved() {
+        format StoreMemory {
+            0x0: sb({{ Mem.ub = Rt<7:0>; }});
+            0x1: sh({{ Mem.uh = Rt<15:0>; }});
+            0x2: swl({{ Mem.ub = Rt<31:0>; }});//,WordAlign);
+            0x3: sw({{ Mem.ub = Rt<31:0>; }});
+            0x6: swr({{ Mem.ub = Rt<31:0>; }});//,WordAlign);
+        }
+
+        format WarnUnimpl {
+            0x7: cache();
+        }
+
+    }
+
+    0x6: decode OPCODE_LO default FailUnimpl::reserved() {
+        0x0: WarnUnimpl::ll();
+
+        format LoadMemory {
+            0x1: lwc1({{ /*F_t<31:0> = Mem.sf; */}});
+            0x5: ldc1({{ /*F_t<63:0> = Mem.df; */}});
+        }
+    }
+
+
+    0x7: decode OPCODE_LO default FailUnimpl::reserved() {
+        0x0: WarnUnimpl::sc();
+
+        format StoreMemory {
+            0x1: swc1({{ //Mem.sf = Ft<31:0>; }});
+            0x5: sdc1({{ //Mem.df = Ft<63:0>; }});
+        }
+    }
+}
+
+
diff --git a/arch/mips/isa/formats.isa b/arch/mips/isa/formats.isa
new file mode 100644
index 000000000..f7a9e4ce2
--- /dev/null
+++ b/arch/mips/isa/formats.isa
@@ -0,0 +1,35 @@
+// -*- mode:c++ -*-
+
+//Templates from this format are used later
+//Include the basic format
+##include "m5/arch/mips/isa/formats/basic.isa"
+
+//Include the basic format
+##include "m5/arch/mips/isa/formats/noop.isa"
+
+//Include utility formats/functions
+##include "m5/arch/mips/isa/formats/util.isa"
+
+//Include the cop0 formats
+##include "m5/arch/mips/isa/formats/cop0.isa"
+
+//Include the integer formats
+##include "m5/arch/mips/isa/formats/int.isa"
+
+//Include the floatOp format
+##include "m5/arch/mips/isa/formats/fp.isa"
+
+//Include the mem format
+##include "m5/arch/mips/isa/formats/mem.isa"
+
+//Include the trap format
+##include "m5/arch/mips/isa/formats/trap.isa"
+
+//Include the branch format
+##include "m5/arch/mips/isa/formats/branch.isa"
+
+//Include the noop format
+##include "m5/arch/mips/isa/formats/unimp.isa"
+
+//Include the noop format
+##include "m5/arch/mips/isa/formats/unknown.isa"
diff --git a/arch/mips/isa/formats/basic.isa b/arch/mips/isa/formats/basic.isa
new file mode 100644
index 000000000..c02af7ddc
--- /dev/null
+++ b/arch/mips/isa/formats/basic.isa
@@ -0,0 +1,66 @@
+// -*- mode:c++ -*-
+
+// Declarations for execute() methods.
+def template BasicExecDeclare {{
+        Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+}};
+
+// Basic instruction class declaration template.
+def template BasicDeclare {{
+        /**
+         * Static instruction class for "%(mnemonic)s".
+         */
+        class %(class_name)s : public %(base_class)s
+        {
+        public:
+                /// Constructor.
+                %(class_name)s(MachInst machInst);
+                %(BasicExecDeclare)s
+    };
+}};
+
+// Basic instruction class constructor template.
+def template BasicConstructor {{
+        inline %(class_name)s::%(class_name)s(MachInst machInst)  : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+        {
+                %(constructor)s;
+        }
+}};
+
+// Basic instruction class execute method template.
+def template BasicExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                Fault fault = NoFault;
+
+                %(fp_enable_check)s;
+                %(op_decl)s;
+                %(op_rd)s;
+                %(code)s;
+
+                if(fault == NoFault)
+                {
+                    %(op_wb)s;
+                }
+                return fault;
+        }
+}};
+
+// Basic decode template.
+def template BasicDecode {{
+        return new %(class_name)s(machInst);
+}};
+
+// Basic decode template, passing mnemonic in as string arg to constructor.
+def template BasicDecodeWithMnemonic {{
+        return new %(class_name)s("%(mnemonic)s", machInst);
+}};
+
+// The most basic instruction format... used only for a few misc. insts
+def format BasicOp(code, *flags) {{
+        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
+}};
diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa
new file mode 100644
index 000000000..0d2ad7855
--- /dev/null
+++ b/arch/mips/isa/formats/branch.isa
@@ -0,0 +1,322 @@
+// -*- mode:c++ -*-
+
+////////////////////////////////////////////////////////////////////
+//
+// Control transfer instructions
+//
+
+output header {{
+
+#include <iostream>
+    using namespace std;
+
+    /**
+     * Base class for instructions whose disassembly is not purely a
+     * function of the machine instruction (i.e., it depends on the
+     * PC).  This class overrides the disassemble() method to check
+     * the PC and symbol table values before re-using a cached
+     * disassembly string.  This is necessary for branches and jumps,
+     * where the disassembly string includes the target address (which
+     * may depend on the PC and/or symbol table).
+     */
+    class PCDependentDisassembly : public MipsStaticInst
+    {
+      protected:
+        /// Cached program counter from last disassembly
+        mutable Addr cachedPC;
+
+        /// Cached symbol table pointer from last disassembly
+        mutable const SymbolTable *cachedSymtab;
+
+        /// Constructor
+        PCDependentDisassembly(const char *mnem, MachInst _machInst,
+                               OpClass __opClass)
+            : MipsStaticInst(mnem, _machInst, __opClass),
+              cachedPC(0), cachedSymtab(0)
+        {
+        }
+
+        const std::string &
+        disassemble(Addr pc, const SymbolTable *symtab) const;
+    };
+
+    /**
+     * Base class for branches (PC-relative control transfers),
+     * conditional or unconditional.
+     */
+    class Branch : public PCDependentDisassembly
+    {
+      protected:
+        /// target address (signed) Displacement .
+        int32_t disp;
+
+        /// Constructor.
+        Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
+            : PCDependentDisassembly(mnem, _machInst, __opClass),
+              disp(OFFSET << 2)
+        {
+            //If Bit 17 is 1 then Sign Extend
+            if ( (disp & 0x00020000) > 0  ) {
+                disp |= 0xFFFE0000;
+            }
+        }
+
+        Addr branchTarget(Addr branchPC) const;
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+
+    /**
+     * Base class for branch likely branches (PC-relative control transfers),
+     */
+    class BranchLikely : public PCDependentDisassembly
+    {
+      protected:
+        /// target address (signed) Displacement .
+        int32_t disp;
+
+        /// Constructor.
+        BranchLikely(const char *mnem, MachInst _machInst, OpClass __opClass)
+            : PCDependentDisassembly(mnem, _machInst, __opClass),
+              disp(OFFSET << 2)
+        {
+
+        }
+
+        Addr branchTarget(Addr branchPC) const;
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+
+    /**
+     * Base class for jumps (register-indirect control transfers).  In
+     * the Mips ISA, these are always unconditional.
+     */
+    class Jump : public PCDependentDisassembly
+    {
+      protected:
+
+        /// Displacement to target address (signed).
+        int32_t disp;
+
+        uint32_t target;
+
+      public:
+        /// Constructor
+        Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
+            : PCDependentDisassembly(mnem, _machInst, __opClass),
+              disp(JMPTARG << 2)
+        {
+        }
+
+        Addr branchTarget(ExecContext *xc) const;
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+}};
+
+output decoder {{
+    Addr
+    Branch::branchTarget(Addr branchPC) const
+    {
+        return branchPC + 4 + disp;
+    }
+
+    Addr
+    BranchLikely::branchTarget(Addr branchPC) const
+    {
+        return branchPC + 4 + disp;
+    }
+
+    Addr
+    Jump::branchTarget(ExecContext *xc) const
+    {
+        Addr NPC = xc->readPC() + 4;
+        uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
+        return (Rb & ~3) | (NPC & 1);
+    }
+
+    const std::string &
+    PCDependentDisassembly::disassemble(Addr pc,
+                                        const SymbolTable *symtab) const
+    {
+        if (!cachedDisassembly ||
+            pc != cachedPC || symtab != cachedSymtab)
+        {
+            if (cachedDisassembly)
+                delete cachedDisassembly;
+
+            cachedDisassembly =
+                new std::string(generateDisassembly(pc, symtab));
+            cachedPC = pc;
+            cachedSymtab = symtab;
+        }
+
+        return *cachedDisassembly;
+    }
+
+    std::string
+    Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        std::stringstream ss;
+
+        ccprintf(ss, "%-10s ", mnemonic);
+
+        // There's only one register arg (RA), but it could be
+        // either a source (the condition for conditional
+        // branches) or a destination (the link reg for
+        // unconditional branches)
+        if (_numSrcRegs == 1) {
+            printReg(ss, _srcRegIdx[0]);
+            ss << ",";
+        } else if(_numSrcRegs == 2) {
+            printReg(ss, _srcRegIdx[0]);
+            ss << ",";
+            printReg(ss, _srcRegIdx[1]);
+            ss << ",";
+        }
+
+        Addr target = pc + 8 + disp;
+
+        std::string str;
+        if (symtab && symtab->findSymbol(target, str))
+            ss << str;
+        else
+            ccprintf(ss, "0x%x", target);
+
+        return ss.str();
+    }
+
+    std::string
+    BranchLikely::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        std::stringstream ss;
+
+        ccprintf(ss, "%-10s ", mnemonic);
+
+        // There's only one register arg (RA), but it could be
+        // either a source (the condition for conditional
+        // branches) or a destination (the link reg for
+        // unconditional branches)
+        if (_numSrcRegs > 0) {
+            printReg(ss, _srcRegIdx[0]);
+            ss << ",";
+        }
+        else if (_numDestRegs > 0) {
+            printReg(ss, _destRegIdx[0]);
+            ss << ",";
+        }
+
+        Addr target = pc + 4 + disp;
+
+        std::string str;
+        if (symtab && symtab->findSymbol(target, str))
+            ss << str;
+        else
+            ccprintf(ss, "0x%x", target);
+
+        return ss.str();
+    }
+
+    std::string
+    Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        std::stringstream ss;
+
+        ccprintf(ss, "%-10s ", mnemonic);
+
+        if ( mnemonic == "jal" ) {
+            Addr npc = pc + 4;
+            ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp);
+        } else if (_numSrcRegs == 0) {
+            std::string str;
+            if (symtab && symtab->findSymbol(disp, str))
+                ss << str;
+            else
+                ccprintf(ss, "0x%x", disp);
+        } else if (_numSrcRegs == 1) {
+             printReg(ss, _srcRegIdx[0]);
+        } else if(_numSrcRegs == 2) {
+            printReg(ss, _srcRegIdx[0]);
+            ss << ",";
+            printReg(ss, _srcRegIdx[1]);
+        } else {
+            panic(">= 3 Source Registers!!!");
+        }
+
+        return ss.str();
+    }
+}};
+
+def format Branch(code,*flags) {{
+    #Add Link Code if Link instruction
+    strlen = len(name)
+    if name[strlen-2:] == 'al':
+        code += 'r31 = NNPC;\n'
+
+    #Condition code
+    code = 'bool cond;\n' + code
+    code += 'if (cond) {\n'
+    code += '  NNPC = NPC + disp;\n'
+    code += '} else {\n'
+    code += '  NNPC = NNPC;\n'
+    code += '} \n'
+
+    code += 'cout << hex << "NPC: " << NPC << " + " << disp << " = " << NNPC << endl;'
+
+    iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
+                        ('IsDirectControl', 'IsCondControl'))
+
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
+}};
+
+
+def format BranchLikely(code,*flags) {{
+    #Add Link Code if Link instruction
+    strlen = len(name)
+    if name[strlen-3:] == 'all':
+        code += 'r31 = NNPC;\n'
+
+    #Condition code
+    code = 'bool cond;\n' + code
+    code += 'if (cond) {'
+    code += 'NNPC = NPC + disp;\n'
+    code += '} \n'
+
+
+    iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
+                        ('IsDirectControl', 'IsCondControl','IsCondDelaySlot'))
+
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
+}};
+
+def format Jump(code,*flags) {{
+    #Add Link Code if Link instruction
+    strlen = len(name)
+    if strlen > 1 and name[1:] == 'al':
+            code = 'r31 = NNPC;\n' + code
+
+    #code += 'if(NNPC == 0x80000638) { NNPC = r31; cout << "SKIPPING JUMP TO SIM_GET_MEM_CONF" << endl;}'
+    #code += 'target = NNPC;'
+
+    iop = InstObjParams(name, Name, 'Jump', CodeBlock(code),\
+                        ('IsIndirectControl', 'IsUncondControl'))
+
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
+}};
+
+
+
+
diff --git a/arch/mips/isa/formats/fp.isa b/arch/mips/isa/formats/fp.isa
new file mode 100644
index 000000000..34b71acf7
--- /dev/null
+++ b/arch/mips/isa/formats/fp.isa
@@ -0,0 +1,49 @@
+// -*- mode:c++ -*-
+
+////////////////////////////////////////////////////////////////////
+//
+// Floating Point operate instructions
+//
+
+output header {{
+        /**
+         * Base class for FP operations.
+         */
+        class FPOp : public MipsStaticInst
+        {
+                protected:
+
+                /// Constructor
+                FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+}};
+
+output decoder {{
+        std::string FPOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+                return "Disassembly of integer instruction\n";
+        }
+}};
+
+
+// Primary format for integer operate instructions:
+def format FloatOp(code, *flags) {{
+        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
+}};
+
+// Primary format for integer operate instructions:
+def format Float64Op(code, *flags) {{
+        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
+}};
diff --git a/arch/mips/isa/formats/int.isa b/arch/mips/isa/formats/int.isa
new file mode 100644
index 000000000..a47844bee
--- /dev/null
+++ b/arch/mips/isa/formats/int.isa
@@ -0,0 +1,130 @@
+// -*- mode:c++ -*-
+
+////////////////////////////////////////////////////////////////////
+//
+// Integer operate instructions
+//
+
+//Outputs to decoder.hh
+output header {{
+#include <iostream>
+    using namespace std;
+        /**
+         * Base class for integer operations.
+         */
+        class IntOp : public MipsStaticInst
+        {
+                protected:
+
+                /// Constructor
+                IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+                                MipsStaticInst(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+
+        class IntImmOp : public MipsStaticInst
+        {
+                protected:
+
+                int32_t imm;
+
+                /// Constructor
+                IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+                                MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM)
+                {
+                    //If Bit 15 is 1 then Sign Extend
+                    int32_t temp = imm & 0x00008000;
+
+                    if (temp > 0 && mnemonic != "lui") {
+                        imm |= 0xFFFF0000;
+                    }
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+
+
+        };
+
+}};
+
+//Outputs to decoder.cc
+output decoder {{
+        std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+            std::stringstream ss;
+
+            ccprintf(ss, "%-10s ", mnemonic);
+
+            // just print the first dest... if there's a second one,
+            // it's generally implicit
+            if (_numDestRegs > 0) {
+                printReg(ss, _destRegIdx[0]);
+            }
+
+            ss << ",";
+
+            // just print the first two source regs... if there's
+            // a third one, it's a read-modify-write dest (Rc),
+            // e.g. for CMOVxx
+            if (_numSrcRegs > 0) {
+                printReg(ss, _srcRegIdx[0]);
+            }
+
+            if (_numSrcRegs > 1) {
+                ss << ",";
+                printReg(ss, _srcRegIdx[1]);
+            }
+
+            return ss.str();
+        }
+
+        std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+            std::stringstream ss;
+
+            ccprintf(ss, "%-10s ", mnemonic);
+
+            if (_numDestRegs > 0) {
+                printReg(ss, _destRegIdx[0]);
+            }
+
+            ss << ",";
+
+            if (_numSrcRegs > 0) {
+                printReg(ss, _srcRegIdx[0]);
+                ss << ",";
+            }
+
+            if( mnemonic == "lui")
+                ccprintf(ss, "%08p ", imm);
+            else
+                ss << (int) imm;
+
+            return ss.str();
+        }
+
+}};
+
+//Used by decoder.isa
+def format IntOp(code, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+
+        # Figure out if we are creating a IntImmOp or a IntOp
+        # by looking at the instruction name
+        iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
+        strlen = len(name)
+        if name[strlen-1] == 'i' or name[strlen-2:] == 'iu':
+            iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags)
+
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = OperateNopCheckDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
+}};
+
+
+
diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa
new file mode 100644
index 000000000..8a07e63d4
--- /dev/null
+++ b/arch/mips/isa/formats/mem.isa
@@ -0,0 +1,469 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+output header {{
+    /**
+     * Base class for general Mips memory-format instructions.
+     */
+    class Memory : public MipsStaticInst
+    {
+      protected:
+
+        /// Memory request flags.  See mem_req_base.hh.
+        unsigned memAccessFlags;
+        /// Pointer to EAComp object.
+        const StaticInstPtr eaCompPtr;
+        /// Pointer to MemAcc object.
+        const StaticInstPtr memAccPtr;
+
+        /// Displacement for EA calculation (signed).
+        int32_t disp;
+
+        /// Constructor
+        Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
+               StaticInstPtr _eaCompPtr = nullStaticInstPtr,
+               StaticInstPtr _memAccPtr = nullStaticInstPtr)
+            : MipsStaticInst(mnem, _machInst, __opClass),
+              memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr),
+              disp(OFFSET)
+        {
+            //If Bit 15 is 1 then Sign Extend
+            int32_t temp = disp & 0x00008000;
+
+            if (temp > 0) {
+                disp |= 0xFFFF0000;
+            }
+        }
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+
+      public:
+
+        const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
+        const StaticInstPtr &memAccInst() const { return memAccPtr; }
+    };
+
+}};
+
+
+output decoder {{
+    std::string
+    Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
+                        flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
+    }
+
+}};
+
+def format LoadAddress(code) {{
+    iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
+}};
+
+
+def template LoadStoreDeclare {{
+    /**
+     * Static instruction class for "%(mnemonic)s".
+     */
+    class %(class_name)s : public %(base_class)s
+    {
+      protected:
+
+        /**
+         * "Fake" effective address computation class for "%(mnemonic)s".
+         */
+        class EAComp : public %(base_class)s
+        {
+          public:
+            /// Constructor
+            EAComp(MachInst machInst);
+
+            %(BasicExecDeclare)s
+        };
+
+        /**
+         * "Fake" memory access instruction class for "%(mnemonic)s".
+         */
+        class MemAcc : public %(base_class)s
+        {
+          public:
+            /// Constructor
+            MemAcc(MachInst machInst);
+
+            %(BasicExecDeclare)s
+        };
+
+      public:
+
+        /// Constructor.
+        %(class_name)s(MachInst machInst);
+
+        %(BasicExecDeclare)s
+
+        %(InitiateAccDeclare)s
+
+        %(CompleteAccDeclare)s
+    };
+}};
+
+
+def template InitiateAccDeclare {{
+    Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+}};
+
+
+def template CompleteAccDeclare {{
+    Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
+}};
+
+
+def template LoadStoreConstructor {{
+    /** TODO: change op_class to AddrGenOp or something (requires
+     * creating new member of OpClass enum in op_class.hh, updating
+     * config files, etc.). */
+    inline %(class_name)s::EAComp::EAComp(MachInst machInst)
+        : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
+    {
+        %(ea_constructor)s;
+    }
+
+    inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
+        : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
+    {
+        %(memacc_constructor)s;
+    }
+
+    inline %(class_name)s::%(class_name)s(MachInst machInst)
+         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+                          new EAComp(machInst), new MemAcc(machInst))
+    {
+        %(constructor)s;
+    }
+}};
+
+
+def template EACompExecute {{
+    Fault
+    %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
+                                   Trace::InstRecord *traceData) const
+    {
+        Addr EA;
+        Fault fault = NoFault;
+
+        %(fp_enable_check)s;
+        %(op_decl)s;
+        %(op_rd)s;
+        %(code)s;
+
+        if (fault == NoFault) {
+            %(op_wb)s;
+            xc->setEA(EA);
+        }
+
+        return fault;
+    }
+}};
+
+def template LoadMemAccExecute {{
+    Fault
+    %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
+                                   Trace::InstRecord *traceData) const
+    {
+        Addr EA;
+        Fault fault = NoFault;
+
+        %(fp_enable_check)s;
+        %(op_decl)s;
+        %(op_rd)s;
+        EA = xc->getEA();
+
+        if (fault == NoFault) {
+            fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
+            %(code)s;
+        }
+
+        if (fault == NoFault) {
+            %(op_wb)s;
+        }
+
+        return fault;
+    }
+}};
+
+
+def template LoadExecute {{
+    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+                                  Trace::InstRecord *traceData) const
+    {
+        Addr EA;
+        Fault fault = NoFault;
+
+        %(fp_enable_check)s;
+        %(op_decl)s;
+        %(op_rd)s;
+        %(ea_code)s;
+
+        if (fault == NoFault) {
+            fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
+            %(memacc_code)s;
+        }
+
+        if (fault == NoFault) {
+            %(op_wb)s;
+        }
+
+        return fault;
+    }
+}};
+
+
+def template LoadInitiateAcc {{
+    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
+                                      Trace::InstRecord *traceData) const
+    {
+        Addr EA;
+        Fault fault = NoFault;
+
+        %(fp_enable_check)s;
+        %(op_src_decl)s;
+        %(op_rd)s;
+        %(ea_code)s;
+
+        if (fault == NoFault) {
+            fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
+        }
+
+        return fault;
+    }
+}};
+
+
+def template LoadCompleteAcc {{
+    Fault %(class_name)s::completeAcc(uint8_t *data,
+                                      %(CPU_exec_context)s *xc,
+                                      Trace::InstRecord *traceData) const
+    {
+        Fault fault = NoFault;
+
+        %(fp_enable_check)s;
+        %(op_src_decl)s;
+        %(op_dest_decl)s;
+
+        memcpy(&Mem, data, sizeof(Mem));
+
+        if (fault == NoFault) {
+            %(memacc_code)s;
+        }
+
+        if (fault == NoFault) {
+            %(op_wb)s;
+        }
+
+        return fault;
+    }
+}};
+
+
+def template StoreMemAccExecute {{
+    Fault
+    %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
+                                   Trace::InstRecord *traceData) const
+    {
+        Addr EA;
+        Fault fault = NoFault;
+        uint64_t write_result = 0;
+
+        %(fp_enable_check)s;
+        %(op_decl)s;
+        %(op_rd)s;
+        EA = xc->getEA();
+
+        if (fault == NoFault) {
+            %(code)s;
+        }
+
+        if (fault == NoFault) {
+            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
+                              memAccessFlags, &write_result);
+            if (traceData) { traceData->setData(Mem); }
+        }
+
+        if (fault == NoFault) {
+            %(postacc_code)s;
+        }
+
+        if (fault == NoFault) {
+            %(op_wb)s;
+        }
+
+        return fault;
+    }
+}};
+
+
+def template StoreExecute {{
+    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+                                  Trace::InstRecord *traceData) const
+    {
+        Addr EA;
+        Fault fault = NoFault;
+        uint64_t write_result = 0;
+
+        %(fp_enable_check)s;
+        %(op_decl)s;
+        %(op_rd)s;
+        %(ea_code)s;
+
+        if (fault == NoFault) {
+            %(memacc_code)s;
+        }
+
+        if (fault == NoFault) {
+            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
+                              memAccessFlags, &write_result);
+            if (traceData) { traceData->setData(Mem); }
+        }
+
+        if (fault == NoFault) {
+            %(postacc_code)s;
+        }
+
+        if (fault == NoFault) {
+            %(op_wb)s;
+        }
+
+        return fault;
+    }
+}};
+
+def template StoreInitiateAcc {{
+    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
+                                      Trace::InstRecord *traceData) const
+    {
+        Addr EA;
+        Fault fault = NoFault;
+        uint64_t write_result = 0;
+
+        %(fp_enable_check)s;
+        %(op_src_decl)s;
+        %(op_dest_decl)s;
+        %(op_rd)s;
+        %(ea_code)s;
+
+        if (fault == NoFault) {
+            %(memacc_code)s;
+        }
+
+        if (fault == NoFault) {
+            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
+                              memAccessFlags, &write_result);
+            if (traceData) { traceData->setData(Mem); }
+        }
+
+        return fault;
+    }
+}};
+
+
+def template StoreCompleteAcc {{
+    Fault %(class_name)s::completeAcc(uint8_t *data,
+                                      %(CPU_exec_context)s *xc,
+                                      Trace::InstRecord *traceData) const
+    {
+        Fault fault = NoFault;
+        uint64_t write_result = 0;
+
+        %(fp_enable_check)s;
+        %(op_dest_decl)s;
+
+        memcpy(&write_result, data, sizeof(write_result));
+
+        if (fault == NoFault) {
+            %(postacc_code)s;
+        }
+
+        if (fault == NoFault) {
+            %(op_wb)s;
+        }
+
+        return fault;
+    }
+}};
+
+// load instructions use Rt as dest, so check for
+// Rt == 31 to detect nops
+def template LoadNopCheckDecode {{
+ {
+     MipsStaticInst *i = new %(class_name)s(machInst);
+     if (RT == 0) {
+         i = makeNop(i);
+     }
+     return i;
+ }
+}};
+
+def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
+                     mem_flags = [], inst_flags = []) {{
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+                      decode_template = LoadNopCheckDecode,
+                      exec_template_base = 'Load')
+}};
+
+
+def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
+                     mem_flags = [], inst_flags = []) {{
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+                      exec_template_base = 'Store')
+}};
+
+//FP loads are offloaded to these formats for now ...
+def format LoadMemory2(ea_code = {{ EA = Rs + disp; }}, memacc_code = {{ }},
+                      mem_flags = [], inst_flags = []) {{
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+                      decode_template = LoadNopCheckDecode,
+                      exec_template_base = 'Load')
+}};
+
+
+//FP stores are offloaded to these formats for now ...
+def format StoreMemory2(ea_code = {{ EA = Rs + disp; }},memacc_code = {{ }},
+                      mem_flags = [], inst_flags = []) {{
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+                      decode_template = LoadNopCheckDecode,
+                      exec_template_base = 'Store')
+}};
+
diff --git a/arch/mips/isa/formats/noop.isa b/arch/mips/isa/formats/noop.isa
new file mode 100644
index 000000000..d35179005
--- /dev/null
+++ b/arch/mips/isa/formats/noop.isa
@@ -0,0 +1,90 @@
+// -*- mode:c++ -*-
+
+////////////////////////////////////////////////////////////////////
+//
+// Nop
+//
+
+output header {{
+    /**
+     * Static instruction class for no-ops.  This is a leaf class.
+     */
+    class Nop : public MipsStaticInst
+    {
+        /// Disassembly of original instruction.
+        const std::string originalDisassembly;
+
+      public:
+        /// Constructor
+        Nop(const std::string _originalDisassembly, MachInst _machInst)
+            : MipsStaticInst("nop", _machInst, No_OpClass),
+              originalDisassembly(_originalDisassembly)
+        {
+            flags[IsNop] = true;
+        }
+
+        ~Nop() { }
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+
+        %(BasicExecDeclare)s
+    };
+}};
+
+output decoder {{
+    std::string Nop::generateDisassembly(Addr pc,
+                                         const SymbolTable *symtab) const
+    {
+#ifdef SS_COMPATIBLE_DISASSEMBLY
+        return originalDisassembly;
+#else
+        return csprintf("%-10s (%s)", "nop", originalDisassembly);
+#endif
+    }
+
+    /// Helper function for decoding nops.  Substitute Nop object
+    /// for original inst passed in as arg (and delete latter).
+    inline
+    MipsStaticInst *
+    makeNop(MipsStaticInst *inst)
+    {
+        MipsStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
+        delete inst;
+        return nop;
+    }
+}};
+
+output exec {{
+    Fault
+    Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
+    {
+        return NoFault;
+    }
+}};
+
+// integer & FP operate instructions use RT as dest, so check for
+// RT == 0 to detect nops
+def template OperateNopCheckDecode {{
+ {
+     MipsStaticInst *i = new %(class_name)s(machInst);
+
+     //if (RD == 0) {
+     //  i = makeNop(i);
+     //}
+
+     return i;
+ }
+}};
+
+
+// Like BasicOperate format, but generates NOP if RC/FC == 31
+def format BasicOperateWithNopCheck(code, *opt_args) {{
+    iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code),
+                        opt_args)
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = OperateNopCheckDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
+}};
+
diff --git a/arch/mips/isa/formats/tlbop.isa b/arch/mips/isa/formats/tlbop.isa
new file mode 100644
index 000000000..f5e4076f2
--- /dev/null
+++ b/arch/mips/isa/formats/tlbop.isa
@@ -0,0 +1,53 @@
+////////////////////////////////////////////////////////////////////
+//
+// TlbOp instructions
+//
+
+output header {{
+        /**
+         * Base class for integer operations.
+         */
+        class TlbOp : public MipsStaticInst
+        {
+                protected:
+
+                /// Constructor
+                TlbOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+}};
+
+output decoder {{
+        std::string TlbOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+                return "Disassembly of integer instruction\n";
+        }
+}};
+
+def template TlbOpExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                //Call into the trap handler with the appropriate fault
+                return No_Fault;
+        }
+
+                //Write the resulting state to the execution context
+                %(op_wb)s;
+
+                return No_Fault;
+        }
+}};
+
+// Primary format for integer operate instructions:
+def format TlbOp(code, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+        iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        exec_output = TlbOpExecute.subst(iop)
+}};
diff --git a/arch/mips/isa/formats/trap.isa b/arch/mips/isa/formats/trap.isa
new file mode 100644
index 000000000..6884d4fa8
--- /dev/null
+++ b/arch/mips/isa/formats/trap.isa
@@ -0,0 +1,52 @@
+////////////////////////////////////////////////////////////////////
+//
+// Trap instructions
+//
+
+output header {{
+        /**
+         * Base class for integer operations.
+         */
+        class Trap : public MipsStaticInst
+        {
+                protected:
+
+                /// Constructor
+                Trap(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+}};
+
+output decoder {{
+        std::string Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+                return "Disassembly of integer instruction\n";
+        }
+}};
+
+def template TrapExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                //Call into the trap handler with the appropriate fault
+                return No_Fault;
+        }
+
+                //Write the resulting state to the execution context
+                %(op_wb)s;
+
+                return No_Fault;
+        }
+}};
+
+// Primary format for integer operate instructions:
+def format Trap(code, *flags) {{
+        code = 'bool cond;\n' + code;
+        iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
+}};
diff --git a/arch/mips/isa/formats/unimp.isa b/arch/mips/isa/formats/unimp.isa
new file mode 100644
index 000000000..adbd5b5b1
--- /dev/null
+++ b/arch/mips/isa/formats/unimp.isa
@@ -0,0 +1,165 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+output header {{
+    /**
+     * Static instruction class for unimplemented instructions that
+     * cause simulator termination.  Note that these are recognized
+     * (legal) instructions that the simulator does not support; the
+     * 'Unknown' class is used for unrecognized/illegal instructions.
+     * This is a leaf class.
+     */
+    class FailUnimplemented : public MipsStaticInst
+    {
+      public:
+        /// Constructor
+        FailUnimplemented(const char *_mnemonic, MachInst _machInst)
+            : MipsStaticInst(_mnemonic, _machInst, No_OpClass)
+        {
+            // don't call execute() (which panics) if we're on a
+            // speculative path
+            flags[IsNonSpeculative] = true;
+        }
+
+        %(BasicExecDeclare)s
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+
+    /**
+     * Base class for unimplemented instructions that cause a warning
+     * to be printed (but do not terminate simulation).  This
+     * implementation is a little screwy in that it will print a
+     * warning for each instance of a particular unimplemented machine
+     * instruction, not just for each unimplemented opcode.  Should
+     * probably make the 'warned' flag a static member of the derived
+     * class.
+     */
+    class WarnUnimplemented : public MipsStaticInst
+    {
+      private:
+        /// Have we warned on this instruction yet?
+        mutable bool warned;
+
+      public:
+        /// Constructor
+        WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
+            : MipsStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
+        {
+            // don't call execute() (which panics) if we're on a
+            // speculative path
+            flags[IsNonSpeculative] = true;
+        }
+
+        %(BasicExecDeclare)s
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+}};
+
+output decoder {{
+    std::string
+    FailUnimplemented::generateDisassembly(Addr pc,
+                                           const SymbolTable *symtab) const
+    {
+        return csprintf("%-10s (unimplemented)", mnemonic);
+    }
+
+    std::string
+    WarnUnimplemented::generateDisassembly(Addr pc,
+                                           const SymbolTable *symtab) const
+    {
+#ifdef SS_COMPATIBLE_DISASSEMBLY
+        return csprintf("%-10s", mnemonic);
+#else
+        return csprintf("%-10s (unimplemented)", mnemonic);
+#endif
+    }
+}};
+
+output exec {{
+    Fault
+    FailUnimplemented::execute(%(CPU_exec_context)s *xc,
+                               Trace::InstRecord *traceData) const
+    {
+        panic("attempt to execute unimplemented instruction '%s' "
+              "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
+        return UnimplementedOpcodeFault;
+    }
+
+    Fault
+    WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
+                               Trace::InstRecord *traceData) const
+    {
+        if (!warned) {
+            warn("instruction '%s' unimplemented\n", mnemonic);
+            warned = true;
+        }
+
+        return NoFault;
+    }
+}};
+
+
+def format FailUnimpl() {{
+    iop = InstObjParams(name, 'FailUnimplemented')
+    decode_block = BasicDecodeWithMnemonic.subst(iop)
+}};
+
+def format WarnUnimpl() {{
+    iop = InstObjParams(name, 'WarnUnimplemented')
+    decode_block = BasicDecodeWithMnemonic.subst(iop)
+}};
+
+output header {{
+    /**
+     * Static instruction class for unknown (illegal) instructions.
+     * These cause simulator termination if they are executed in a
+     * non-speculative mode.  This is a leaf class.
+     */
+    class Unknown : public MipsStaticInst
+    {
+      public:
+        /// Constructor
+        Unknown(MachInst _machInst)
+            : MipsStaticInst("unknown", _machInst, No_OpClass)
+        {
+            // don't call execute() (which panics) if we're on a
+            // speculative path
+            flags[IsNonSpeculative] = true;
+        }
+
+        %(BasicExecDeclare)s
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+}};
+
diff --git a/arch/mips/isa/formats/unknown.isa b/arch/mips/isa/formats/unknown.isa
new file mode 100644
index 000000000..4601b3684
--- /dev/null
+++ b/arch/mips/isa/formats/unknown.isa
@@ -0,0 +1,52 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+output decoder {{
+    std::string
+    Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
+                        "unknown", machInst, OPCODE);
+    }
+}};
+
+output exec {{
+    Fault
+    Unknown::execute(%(CPU_exec_context)s *xc,
+                     Trace::InstRecord *traceData) const
+    {
+        panic("attempt to execute unknown instruction "
+              "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
+        return UnimplementedOpcodeFault;
+    }
+}};
+
+def format Unknown() {{
+    decode_block = 'return new Unknown(machInst);\n'
+}};
+
diff --git a/arch/mips/isa/formats/util.isa b/arch/mips/isa/formats/util.isa
new file mode 100644
index 000000000..db4bf204a
--- /dev/null
+++ b/arch/mips/isa/formats/util.isa
@@ -0,0 +1,148 @@
+// -*- mode:c++ -*-
+
+let {{
+def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+                  postacc_code = '', base_class = 'Memory',
+                  decode_template = BasicDecode, exec_template_base = ''):
+    # Make sure flags are in lists (convert to lists if not).
+    mem_flags = makeList(mem_flags)
+    inst_flags = makeList(inst_flags)
+
+    # add hook to get effective addresses into execution trace output.
+    ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
+
+    # generate code block objects
+    ea_cblk = CodeBlock(ea_code)
+    memacc_cblk = CodeBlock(memacc_code)
+    postacc_cblk = CodeBlock(postacc_code)
+
+    # Some CPU models execute the memory operation as an atomic unit,
+    # while others want to separate them into an effective address
+    # computation and a memory access operation.  As a result, we need
+    # to generate three StaticInst objects.  Note that the latter two
+    # are nested inside the larger "atomic" one.
+
+    # generate InstObjParams for EAComp object
+    ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags)
+
+    # generate InstObjParams for MemAcc object
+    memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags)
+    # in the split execution model, the MemAcc portion is responsible
+    # for the post-access code.
+    memacc_iop.postacc_code = postacc_cblk.code
+
+    # generate InstObjParams for InitiateAcc, CompleteAcc object
+    # The code used depends on the template being used
+    if (exec_template_base == 'Load'):
+        initiateacc_cblk = CodeBlock(ea_code + memacc_code)
+        completeacc_cblk = CodeBlock(memacc_code + postacc_code)
+    elif (exec_template_base == 'Store'):
+        initiateacc_cblk = CodeBlock(ea_code + memacc_code)
+        completeacc_cblk = CodeBlock(postacc_code)
+    else:
+        initiateacc_cblk = ''
+        completeacc_cblk = ''
+
+    initiateacc_iop = InstObjParams(name, Name, base_class, initiateacc_cblk,
+                                    inst_flags)
+
+    completeacc_iop = InstObjParams(name, Name, base_class, completeacc_cblk,
+                                    inst_flags)
+
+    if (exec_template_base == 'Load'):
+        initiateacc_iop.ea_code = ea_cblk.code
+        initiateacc_iop.memacc_code = memacc_cblk.code
+        completeacc_iop.memacc_code = memacc_cblk.code
+        completeacc_iop.postacc_code = postacc_cblk.code
+    elif (exec_template_base == 'Store'):
+        initiateacc_iop.ea_code = ea_cblk.code
+        initiateacc_iop.memacc_code = memacc_cblk.code
+        completeacc_iop.postacc_code = postacc_cblk.code
+
+    # generate InstObjParams for unified execution
+    cblk = CodeBlock(ea_code + memacc_code + postacc_code)
+    iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
+
+    iop.ea_constructor = ea_cblk.constructor
+    iop.ea_code = ea_cblk.code
+    iop.memacc_constructor = memacc_cblk.constructor
+    iop.memacc_code = memacc_cblk.code
+    iop.postacc_code = postacc_cblk.code
+
+    if mem_flags:
+        s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
+        iop.constructor += s
+        memacc_iop.constructor += s
+
+    # select templates
+    memAccExecTemplate = eval(exec_template_base + 'MemAccExecute')
+    fullExecTemplate = eval(exec_template_base + 'Execute')
+    initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
+    completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
+
+    # (header_output, decoder_output, decode_block, exec_output)
+    return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop),
+            decode_template.subst(iop),
+            EACompExecute.subst(ea_iop)
+            + memAccExecTemplate.subst(memacc_iop)
+            + fullExecTemplate.subst(iop)
+            + initiateAccTemplate.subst(initiateacc_iop)
+            + completeAccTemplate.subst(completeacc_iop))
+}};
+
+
+output exec {{
+
+using namespace MipsISA;
+
+
+    /// CLEAR ALL CPU INST/EXE HAZARDS
+    inline void
+    clear_exe_inst_hazards()
+    {
+        //CODE HERE
+    }
+
+
+    /// Check "FP enabled" machine status bit.  Called when executing any FP
+    /// instruction in full-system mode.
+    /// @retval Full-system mode: NoFault if FP is enabled, FenFault
+    /// if not.  Non-full-system mode: always returns NoFault.
+#if FULL_SYSTEM
+    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
+    {
+        Fault fault = NoFault;	// dummy... this ipr access should not fault
+        if (!Mips34k::ICSR_FPE(xc->readIpr(MipsISA::IPR_ICSR, fault))) {
+            fault = FloatEnableFault;
+        }
+        return fault;
+    }
+#else
+    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
+    {
+        return NoFault;
+    }
+#endif
+
+    double convert_and_round(float w, int x, int y, int z)
+    {
+        double temp = .34000;
+
+        return temp;
+    }
+
+    enum FPTypes{
+        FP_SINGLE,
+        FP_DOUBLE,
+        FP_LONG,
+        FP_PS_LO,
+        FP_PS_HI,
+        FP_WORD,
+        RND_NEAREST,
+        RND_ZERO,
+        RND_UP,
+        RND_DOWN
+    };
+}};
+
+
diff --git a/arch/mips/isa/includes.isa b/arch/mips/isa/includes.isa
new file mode 100644
index 000000000..da919be00
--- /dev/null
+++ b/arch/mips/isa/includes.isa
@@ -0,0 +1,39 @@
+////////////////////////////////////////////////////////////////////
+//
+// Output include file directives.
+//
+
+output header {{
+#include <sstream>
+#include <iostream>
+#include <iomanip>
+
+#include "cpu/static_inst.hh"
+#include "mem/mem_req.hh"  // some constructors use MemReq flags
+}};
+
+output decoder {{
+#include "base/cprintf.hh"
+#include "base/loader/symtab.hh"
+#include "cpu/exec_context.hh"  // for Jump::branchTarget()
+
+#include <math.h>
+#if defined(linux)
+#include <fenv.h>
+#endif
+}};
+
+output exec {{
+#include <math.h>
+#if defined(linux)
+#include <fenv.h>
+#endif
+
+#ifdef FULL_SYSTEM
+//#include "arch/alpha/pseudo_inst.hh"
+#endif
+#include "cpu/base.hh"
+#include "cpu/exetrace.hh"
+#include "sim/sim_exit.hh"
+}};
+
diff --git a/arch/mips/isa/main.isa b/arch/mips/isa/main.isa
new file mode 100644
index 000000000..411e398b4
--- /dev/null
+++ b/arch/mips/isa/main.isa
@@ -0,0 +1,52 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+##include "m5/arch/mips/isa/includes.isa"
+
+////////////////////////////////////////////////////////////////////
+//
+// Namespace statement.  Everything below this line will be in the
+// MipsISAInst namespace.
+//
+
+namespace MipsISA;
+
+//Include the bitfield definitions
+##include "m5/arch/mips/isa/bitfields.isa"
+
+//Include the operand_types and operand definitions
+##include "m5/arch/mips/isa/operands.isa"
+
+//Include the base class for mips instructions, and some support code
+##include "m5/arch/mips/isa/base.isa"
+
+//Include the definitions for the instruction formats
+##include "m5/arch/mips/isa/formats.isa"
+
+//Include the decoder definition
+##include "m5/arch/mips/isa/decoder.isa"
diff --git a/arch/mips/isa/operands.isa b/arch/mips/isa/operands.isa
new file mode 100644
index 000000000..13870337b
--- /dev/null
+++ b/arch/mips/isa/operands.isa
@@ -0,0 +1,33 @@
+def operand_types {{
+    'sb' : ('signed int', 8),
+    'ub' : ('unsigned int', 8),
+    'sh' : ('signed int', 16),
+    'uh' : ('unsigned int', 16),
+    'sw' : ('signed int', 32),
+    'uw' : ('unsigned int', 32),
+    'sd' : ('signed int', 64),
+    'ud' : ('unsigned int', 64),
+    'sf' : ('float', 32),
+    'df' : ('float', 64),
+    'qf' : ('float', 128)
+}};
+
+def operands {{
+    'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
+    'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
+    'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
+    'r31': ('IntReg', 'uw','R31','IsInteger', 4),
+    'R0':  ('IntReg', 'uw','R0', 'IsInteger', 5),
+
+    'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
+
+    'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
+    'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
+    'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
+    'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
+
+    'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
+
+    'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
+    'NNPC':('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
+}};