Start working on more complex FP tests

Debug FP instructions to handle these FP insts

arch/mips/isa/bitfields.isa:
    add Bitfield for Floating Point Condition Codes
arch/mips/isa/decoder.isa:
    Follow instruction naming style with FP single insts
    Send the float value to the convert&round functions in single FP
    add ll inst support
    add 'token' sc support
arch/mips/isa_traits.cc:
    Add SINGLE->WORD, WORD->SINGLE, & WORD->DOUBLE conversions
arch/mips/regfile.hh:
    update header files
arch/mips/regfile/float_regfile.hh:
    Add more FP registers

--HG--
rename : arch/mips/int_regfile.hh => arch/mips/regfile/int_regfile.hh
rename : arch/mips/misc_regfile.hh => arch/mips/regfile/misc_regfile.hh
extra : convert_revision : 92faf0bfd8542ade762ac569ec158d198f6a9c7e

2 files changed, 26 insertions, 27 deletions

diff --git a/arch/mips/isa/bitfields.isa b/arch/mips/isa/bitfields.isa
index eb917595c..e1124a591 100644
--- a/arch/mips/isa/bitfields.isa
+++ b/arch/mips/isa/bitfields.isa
@@ -39,7 +39,6 @@ def bitfield FT	      <20:16>;
 def bitfield FS	      <15:11>;
 def bitfield FD	      <10:6>;
 
-def bitfield CC       <20:18>;
 def bitfield ND       <17:17>;
 def bitfield TF       <16:16>;
 def bitfield MOVCI    <16:16>;
@@ -48,6 +47,10 @@ def bitfield SRL      <21:21>;
 def bitfield SRLV     < 6: 6>;
 def bitfield SA       <10: 6>;
 
+// Floating Point Condition Codes
+def bitfield CC <10:8>;
+def bitfield BRANCH_CC <20:18>;
+
 // CP0 Register Select
 def bitfield SEL       < 2: 0>;
 
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index 53bbb94a4..d2d14efd0 100644
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -500,51 +500,51 @@ decode OPCODE_HI default Unknown::unknown() {
                     0x0: decode FUNCTION_HI {
                         0x0: decode FUNCTION_LO {
                             format FloatOp {
-                                0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}});
-                                0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}});
-                                0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}});
-                                0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}});
-                                0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}});
-                                0x5: abss({{ Fd.sf = fabs(Fs.sf);}});
-                                0x6: movs({{ Fd.sf = Fs.sf;}});
-                                0x7: negs({{ Fd.sf = -1 * Fs.sf;}});
+                                0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}});
+                                0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}});
+                                0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}});
+                                0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}});
+                                0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}});
+                                0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}});
+                                0x6: mov_s({{ Fd.sf = Fs.sf;}});
+                                0x7: neg_s({{ Fd.sf = -1 * Fs.sf;}});
                             }
                         }
 
                         0x1: decode FUNCTION_LO {
                             format Float64Op {
                                 0x0: round_l_s({{
-                                    Fd = convert_and_round(Fs.uw, SINGLE_TO_LONG, RND_NEAREST);
+                                    Fd.ud = convert_and_round(Fs.sf, SINGLE_TO_LONG, RND_NEAREST);
                                 }});
 
                                 0x1: trunc_l_s({{
-                                    Fd = convert_and_round(Fs.uw, SINGLE_TO_LONG, RND_ZERO);
+                                    Fd.ud = convert_and_round(Fs.sf, SINGLE_TO_LONG, RND_ZERO);
                                 }});
 
                                 0x2: ceil_l_s({{
-                                    Fd = convert_and_round(Fs.uw, SINGLE_TO_LONG, RND_UP);
+                                    Fd.ud = convert_and_round(Fs.sf, SINGLE_TO_LONG, RND_UP);
                                 }});
 
                                 0x3: floor_l_s({{
-                                    Fd = convert_and_round(Fs.uw, SINGLE_TO_LONG, RND_DOWN);
+                                    Fd.ud = convert_and_round(Fs.sf, SINGLE_TO_LONG, RND_DOWN);
                                 }});
                             }
 
                             format FloatOp {
                                 0x4: round_w_s({{
-                                    Fd = convert_and_round(Fs.uw, SINGLE_TO_WORD, RND_NEAREST);
+                                    Fd.uw = convert_and_round(Fs.sf, SINGLE_TO_WORD, RND_NEAREST);
                                 }});
 
                                 0x5: trunc_w_s({{
-                                    Fd = convert_and_round(Fs.uw, SINGLE_TO_WORD, RND_ZERO);
+                                    Fd.uw = convert_and_round(Fs.sf, SINGLE_TO_WORD, RND_ZERO);
                                 }});
 
                                 0x6: ceil_w_s({{
-                                    Fd = convert_and_round(Fs.uw, SINGLE_TO_WORD, RND_UP);
+                                    Fd.uw = convert_and_round(Fs.sf, SINGLE_TO_WORD, RND_UP);
                                 }});
 
                                 0x7: floor_w_s({{
-                                    Fd = convert_and_round(Fs.uw, SINGLE_TO_WORD, RND_DOWN);
+                                    Fd.uw = convert_and_round(Fs.sf, SINGLE_TO_WORD, RND_DOWN);
                                 }});
                             }
                         }
@@ -578,7 +578,7 @@ decode OPCODE_HI default Unknown::unknown() {
 
                                 0x4: cvt_w_s({{
                                     int rnd_mode = xc->readMiscReg(FCSR) & 0x03;
-                                    Fd.uw = convert_and_round(Fs.uw, SINGLE_TO_WORD, rnd_mode);
+                                    Fd.uw = convert_and_round(Fs.sf, SINGLE_TO_WORD, rnd_mode);
                                 }});
                             }
 
@@ -586,7 +586,7 @@ decode OPCODE_HI default Unknown::unknown() {
                             format Float64Op {
                                 0x5: cvt_l_s({{
                                     int rnd_mode = xc->readMiscReg(FCSR) & 0x03;
-                                    Fd.ud = convert_and_round(Fs.uw, SINGLE_TO_LONG, rnd_mode);
+                                    Fd.ud = convert_and_round(Fs.sf, SINGLE_TO_LONG, rnd_mode);
                                 }});
 
                                 0x6: cvt_ps_st({{
@@ -696,12 +696,12 @@ decode OPCODE_HI default Unknown::unknown() {
                         format FloatOp {
                             0x20: cvt_s_w({{
                                 int rnd_mode = xc->readMiscReg(FCSR) & 0x03;
-                                Fd.uw = convert_and_round(Fs.uw, WORD_TO_SINGLE, rnd_mode);
+                                Fd.uw = convert_and_round(Fs.sf, WORD_TO_SINGLE, rnd_mode);
                             }});
 
                             0x21: cvt_d_w({{
                                 int rnd_mode = xc->readMiscReg(FCSR) & 0x03;
-                                Fd.ud = convert_and_round(Fs.uw, WORD_TO_DOUBLE, rnd_mode);
+                                Fd.ud = convert_and_round(Fs.sf, WORD_TO_DOUBLE, rnd_mode);
                             }});
                         }
                     }
@@ -1033,8 +1033,6 @@ decode OPCODE_HI default Unknown::unknown() {
                 uint32_t unalign_addr = Rs + disp;
                 uint32_t offset = unalign_addr & 0x00000003;
 #if BYTE_ORDER == BIG_ENDIAN
-                std::cout << "Big Endian Byte Order\n";
-
                 switch(offset)
                 {
                   case 0:
@@ -1060,8 +1058,6 @@ decode OPCODE_HI default Unknown::unknown() {
                     panic("lwl: bad offset");
                 }
 #elif BYTE_ORDER == LITTLE_ENDIAN
-                std::cout << "Little Endian Byte Order\n";
-
                 switch(offset)
                 {
                   case 0:
@@ -1274,7 +1270,7 @@ decode OPCODE_HI default Unknown::unknown() {
     }
 
     0x6: decode OPCODE_LO default FailUnimpl::reserved() {
-        0x0: FailUnimpl::ll();
+        0x0: LoadMemory::ll({{Rt.uw = Mem.uw}},mem_flags=LOCKED);
 
         format LoadFloatMemory {
             0x1: lwc1({{ Ft.uw = Mem.uw;    }});
@@ -1284,7 +1280,7 @@ decode OPCODE_HI default Unknown::unknown() {
 
 
     0x7: decode OPCODE_LO default FailUnimpl::reserved() {
-        0x0: FailUnimpl::sc();
+        0x0: StoreMemory::sc({{ Mem.uw = Rt.uw; Rt.uw = 1; }});
 
         format StoreFloatMemory {
             0x1: swc1({{ Mem.uw = Ft.uw; }});