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| author | Korey Sewell <ksewell@umich.edu> | 2006-05-07 13:26:15 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2006-05-07 13:26:15 -0400 |
| commit | a7565418d297043bf28fa8d9e1efaabb5c4faf07 (patch) | |
| tree | f5a7df1cbbf9ef423deb786e7240c2a03a7fa4aa /arch/mips/isa | |
| parent | 34a5732bd3c6a146a62757a50d59b7960c41fc5f (diff) | |
| download | gem5-a7565418d297043bf28fa8d9e1efaabb5c4faf07.tar.xz | |
Basic MIPS floating point test works now ... I had to realize that when using the double FP reg the
register with the higher # contains the most significant bytes...
arch/mips/isa/decoder.isa:
divide instruction fixes
arch/mips/isa_traits.cc:
use double as argument to cvt & round function.
clean up cout statements in function.
arch/mips/isa_traits.hh:
In MIPS the higher # reg of a doubles pair is ALSO the most significant reg.
Once I switched this the basic MIPS FP test I had worked.
--HG--
extra : convert_revision : 45c80df229e6174d0b52fc7cfb530642b1f1fc35
Diffstat (limited to 'arch/mips/isa')
| -rw-r--r-- | arch/mips/isa/decoder.isa | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa index 9bafe9f34..53bbb94a4 100644 --- a/arch/mips/isa/decoder.isa +++ b/arch/mips/isa/decoder.isa @@ -149,13 +149,13 @@ decode OPCODE_HI default Unknown::unknown() { }}); 0x2: div({{ - xc->setMiscReg(Hi,Rs.sw % Rt.sw); - xc->setMiscReg(Lo,Rs.sw / Rt.sw); + xc->setMiscReg(Hi,Rs.sd % Rt.sd); + xc->setMiscReg(Lo,Rs.sd / Rt.sd); }}); 0x3: divu({{ - xc->setMiscReg(Hi,Rs.uw % Rt.uw); - xc->setMiscReg(Lo,Rs.uw / Rt.uw); + xc->setMiscReg(Hi,Rs.ud % Rt.ud); + xc->setMiscReg(Lo,Rs.ud / Rt.ud); }}); } } @@ -435,6 +435,7 @@ decode OPCODE_HI default Unknown::unknown() { 0x6: ctc1({{ uint32_t fcsr_reg = xc->readMiscReg(FCSR); uint32_t temp; + switch (FS) { case 25: |