FP programs are back to running... Condition Codes can be read and set...

Special Regs (Hi,Lo,FCSR) are now added to the operands for use in decoder.isa.

Now it's back to just debugging execution of code for the release (those unaligned
memory access instruction pairs are still quite the pain i might add)

arch/mips/isa_traits.hh:
    declare functions for .cc file
arch/mips/isa_traits.cc:
    delete unnecessary overloaded functions

    implement condition code functions

    implement round function
arch/mips/isa/base.isa:
    remove R31 constant... define in the operands.isa file instead
arch/mips/isa/decoder.isa:
    wholesale changes once again to FP.

    Now the FP Condition Codes are implemented and the FP programs can
    run and complete to finish.

    Use isnan() instead of my unorderedFP() function

    Also, we now access special regs such as HI,LO,FCSR,etc. just like we do any other reg. operand
arch/mips/isa/operands.isa:
    add more operands for special control regs in int and FP regfiles
arch/mips/isa/formats/branch.isa:
    use R31 instead of r31
arch/mips/isa/formats/fp.isa:
    use MakeCCVector to set Condition Codes in FCSR
arch/mips/regfile/float_regfile.hh:
    treat control regs like any other reg. Just Index them after the regular architectural registers
arch/mips/regfile/int_regfile.hh:
    treat hi,lo as regular int. regs w/special indexing
arch/mips/regfile/regfile.hh:
    no longer need for special register accesses with their own function.

--HG--
rename : arch/mips/regfile.hh => arch/mips/regfile/regfile.hh
extra : convert_revision : 5d2f8fdb59606de2b2e9db3e0a085240561e479e

1 files changed, 15 insertions, 47 deletions

diff --git a/arch/mips/isa_traits.cc b/arch/mips/isa_traits.cc
index 19ef46291..216a6e2ec 100644
--- a/arch/mips/isa_traits.cc
+++ b/arch/mips/isa_traits.cc
@@ -96,41 +96,15 @@ MipsISA::fpConvert(double fp_val, ConvertType cvt_type)
     }
 }
 
-float
-MipsISA::roundFP(float val)
-{
-    return 1.5;
-}
-
-float
-MipsISA::roundFP(uint64_t val)
-{
-    return 1.5;
-}
-
 double
-MipsISA::roundFP(double val)
+MipsISA::roundFP(double val, int digits)
 {
-    double trunc_val = trunc(val);
-    double fraction = val - trunc_val;
-
-    if (fraction < 0.5)
-        return val;
-    else
-        return val + 1;
-}
-
-float
-MipsISA::truncFP(float val)
-{
-    return 1.0;
-}
-
-double
-MipsISA::truncFP(uint64_t val)
-{
-    int trunc_val = (int) val;
-    return (double) trunc_val;
+    double digit_offset = pow(10.0,digits);
+    val = val * digit_offset;
+    val = val + 0.5;
+    val = floor(val);
+    val = val / digit_offset;
+    return val;
 }
 
 double
@@ -141,26 +115,20 @@ MipsISA::truncFP(double val)
 }
 
 bool
-MipsISA::unorderedFP(float val)
+MipsISA::getFPConditionCode(uint32_t fcsr_reg, int cc)
 {
-    return false;
+    //uint32_t cc_bits = xc->readFloatReg(35);
+    return false;//regFile.floatRegfile.getConditionCode(cc);
 }
 
-bool
-MipsISA::unorderedFP(double val)
+uint32_t
+MipsISA::makeCCVector(uint32_t fcsr, int num, bool val)
 {
-    return false;
-}
+    int shift = (num == 0) ? 22 : num + 23;
 
-bool
-MipsISA::getFPConditionCode(int cc)
-{
-    return false;
-}
+    fcsr = fcsr | (val << shift);
 
-void
-MipsISA::setFPConditionCode(int num, bool val)
-{
+    return fcsr;
 }
 
 #if FULL_SYSTEM