Finally MIPS does hello world!

arch/mips/isa/bitfields.isa:
    add RS_SRL bitfield ...these must be set to 0 for a SRL instruction
arch/mips/isa/decoder.isa:
    Make unimplemented instructions Fail instead of just Warn
    Edits to SRA & SRAV instructions
    Implement CFC1 instructions
    Unaligned Memory Access Support (Maybe Not fully functional yet)
    Enforce a more strict decode policy (in terms of different bitfields set to 0 on certain instructions)
arch/mips/isa/formats/branch.isa:
    Fix disassembly
arch/mips/isa/formats/int.isa:
    Add sign extend Immediate and zero extend Immediate to Int class.
    Probably a bit unnecessary in the long run since these manipulations could
    be done in the actually instruction instead of keep a int value
arch/mips/isa/formats/mem.isa:
    Comment/Remove out split-memory access code... revisit this after SimpleCPU works
arch/mips/isa/formats/unimp.isa:
    Add inst2string function to Unimplemented panic. PRints out the instruction
    binary to help in debuggin
arch/mips/isa/formats/unknown.isa:
    define inst2string function , use in unknown disassembly and panic function
arch/mips/isa/operands.isa:
    Make "Mem" default to a unsigned word since this is MIPS32
arch/mips/isa_traits.hh:
    change return values to 32 instead of 64
arch/mips/linux_process.cc:
    assign some syscalls to the right functions
cpu/static_inst.hh:
    more debug functions for MIPS (these will be move to the mips directory soon)
mem/page_table.cc:
mem/page_table.hh:
    toward a better implementation for unaligned memory access
mem/request.hh:
    NO ALIGN FAULT flag added to support unaligned memory access
sim/syscall_emul.cc:
    additional SyscallVerbose comments

--HG--
extra : convert_revision : 1987d80c9f4ede507f1f0148435e0bee97d2428c

1 files changed, 10 insertions, 15 deletions

diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh
index 486a5d130..fd6f6e5c7 100644
--- a/arch/mips/isa_traits.hh
+++ b/arch/mips/isa_traits.hh
@@ -61,7 +61,7 @@ class SyscallReturn {
            template <class T>
            SyscallReturn(T v, bool s)
            {
-               retval = (uint64_t)v;
+               retval = (uint32_t)v;
                success = s;
            }
 
@@ -69,7 +69,7 @@ class SyscallReturn {
            SyscallReturn(T v)
            {
                success = (v >= 0);
-               retval = (uint64_t)v;
+               retval = (uint32_t)v;
            }
 
            ~SyscallReturn() {}
@@ -137,7 +137,7 @@ namespace MipsISA
 
     const int SyscallNumReg = ReturnValueReg1;
     const int SyscallPseudoReturnReg = ReturnValueReg1;
-    const int SyscallSuccessReg = ReturnValueReg1;
+    const int SyscallSuccessReg = ArgumentReg3;
 
     const int LogVMPageSize = 13;	// 8K bytes
     const int VMPageSize = (1 << LogVMPageSize);
@@ -162,7 +162,7 @@ namespace MipsISA
         MiscReg_DepTag = 67
     };
 
-    typedef uint64_t IntReg;
+    typedef uint32_t IntReg;
     typedef IntReg IntRegFile[NumIntRegs];
 
 /* floating point register file entry type
@@ -240,7 +240,7 @@ namespace MipsISA
 
     // cop-0/cop-1 system control register file
     typedef uint64_t MiscReg;
-//typedef MiscReg MiscRegFile[NumMiscRegs];
+    //typedef MiscReg MiscRegFile[NumMiscRegs];
     class MiscRegFile {
 
       protected:
@@ -451,6 +451,7 @@ namespace MipsISA
         Hi,
         Lo,
         FCSR,
+        FIR,
         FPCR,
 
         //Alpha Regs, but here now, for
@@ -589,21 +590,15 @@ extern const Addr PageOffset;
 
     static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
     {
-        // check for error condition.  Alpha syscall convention is to
-        // indicate success/failure in reg a3 (r19) and put the
-        // return value itself in the standard return value reg (v0).
         if (return_value.successful()) {
             // no error
-            regs->intRegFile[ReturnValueReg1] = 0;
-            regs->intRegFile[ReturnValueReg2] = return_value.value();
+            regs->intRegFile[SyscallSuccessReg] = 0;
+            regs->intRegFile[ReturnValueReg1] = return_value.value();
         } else {
             // got an error, return details
-            regs->intRegFile[ReturnValueReg1] = (IntReg) -1;
-            regs->intRegFile[ReturnValueReg2] = -return_value.value();
+            regs->intRegFile[SyscallSuccessReg] = (IntReg) -1;
+            regs->intRegFile[ReturnValueReg1] = -return_value.value();
         }
-
-        //regs->intRegFile[ReturnValueReg1] = (IntReg)return_value;
-        //panic("Returning from syscall\n");
     }
 
     // Machine operations