Support NNPC and branch instructions ... Outputs to decoder.cc correctly

Edits to the CPU model may still need to be made to handle branch likely insts...

arch/isa_parser.py:
    add a NNPC operand ...
arch/mips/isa/base.isa:
    change SPARC to MIPS
arch/mips/isa/decoder.isa:
    typo < to >=
arch/mips/isa/formats/basic.isa:
    spacing
arch/mips/isa/formats/branch.isa:
    add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
    support for NNPC and R31
arch/mips/isa_traits.hh:
    NNPC Addr variable

--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad

1 files changed, 2 insertions, 0 deletions

diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh
index 55e9c0dcb..e171737a3 100644
--- a/arch/mips/isa_traits.hh
+++ b/arch/mips/isa_traits.hh
@@ -430,6 +430,8 @@ class MipsISA
 
                 Addr pc;		// Program Counter
                 Addr npc;		// Next Program Counter
+            Addr nnpc;                  // Next next program Counter
+
 
                 void serialize(std::ostream &os);
                 void unserialize(Checkpoint *cp, const std::string &section);