MIPS is back to compiling and building now!

arch/alpha/isa_traits.hh:
    used for SimpleCPU instead of explicitly calling the namespace we declare in isa_traits.hhs
    so other archs. can use SimpleCPU
arch/mips/SConscript:
    dont include common_syscall or tru64
arch/mips/faults.cc:
arch/mips/faults.hh:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
    Change Faults to new format
arch/mips/isa/decoder.isa:
    Fix readMiscReg access
    Made change so that you cant explicitly tell if a instruction nop,ehb,or ssnop... These are all variants
    of the sll instruction so I may need to make a separte class of instructions to handle thse better
arch/mips/isa/includes.isa:
    add isa_traits.hh and MipsISA included into every auto-gen file
arch/mips/isa_traits.cc:
    create copyMiscRegs function...
    delete useless code
arch/mips/isa_traits.hh:
    clean up for build
arch/mips/linux_process.cc:
    mem is now getMemPort(), linux process objects now take in a system argument
arch/mips/linux_process.hh:
    new argument for linux process
arch/mips/process.cc:
    add system
arch/mips/process.hh:
    add system variable
cpu/cpu_exec_context.cc:
    Change AlphaISA to TheISA
cpu/exec_context.hh:
    add readNextNPC and setNextNPC functions
cpu/simple/cpu.cc:
    include isa_traits for namespace declariation
cpu/simple/cpu.hh:
    PC & NPC access/modify functions
arch/mips/utility.hh:
    file needed for compile

--HG--
extra : convert_revision : 29a327e79c51c6174a6e526aa68c7aab7e7eb535

1 files changed, 78 insertions, 46 deletions

diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh
index 1dfa0dc7a..4850010d4 100644
--- a/arch/mips/isa_traits.hh
+++ b/arch/mips/isa_traits.hh
@@ -54,12 +54,48 @@ int DTB_ASN_ASN(uint64_t reg);
 int ITB_ASN_ASN(uint64_t reg);
 };
 
+#if !FULL_SYSTEM
+class SyscallReturn {
+        public:
+           template <class T>
+           SyscallReturn(T v, bool s)
+           {
+               retval = (uint64_t)v;
+               success = s;
+           }
+
+           template <class T>
+           SyscallReturn(T v)
+           {
+               success = (v >= 0);
+               retval = (uint64_t)v;
+           }
+
+           ~SyscallReturn() {}
+
+           SyscallReturn& operator=(const SyscallReturn& s) {
+               retval = s.retval;
+               success = s.success;
+               return *this;
+           }
+
+           bool successful() { return success; }
+           uint64_t value() { return retval; }
+
+
+       private:
+           uint64_t retval;
+           bool success;
+};
+#endif
+
 namespace MipsISA
 {
     typedef uint32_t MachInst;
-//  typedef uint64_t Addr;
+    typedef uint32_t MachInst;
+    typedef uint64_t ExtMachInst;
     typedef uint8_t  RegIndex;
-
+//  typedef uint64_t Addr;
     enum {
         MemoryEnd = 0xffffffffffffffffULL,
 
@@ -87,7 +123,9 @@ namespace MipsISA
         ArgumentReg3 = 19,
         ArgumentReg4 = 20,
         ArgumentReg5 = 21,
-
+        SyscallNumReg = ReturnValueReg,
+        SyscallPseudoReturnReg = ArgumentReg4,
+        SyscallSuccessReg = 19,
         LogVMPageSize = 13,	// 8K bytes
         VMPageSize = (1 << LogVMPageSize),
 
@@ -129,8 +167,7 @@ namespace MipsISA
     typedef uint64_t MiscReg;
 //typedef MiscReg MiscRegFile[NumMiscRegs];
     class MiscRegFile {
-      public:
-        MiscReg
+
       protected:
         uint64_t	fpcr;		// floating point condition codes
         uint64_t	uniq;		// process-unique register
@@ -145,6 +182,8 @@ namespace MipsISA
         int getInstAsid();
         int getDataAsid();
 
+        void copyMiscRegs(ExecContext *xc);
+
         MiscReg readReg(int misc_reg)
         { return miscRegFile[misc_reg]; }
 
@@ -159,7 +198,7 @@ namespace MipsISA
         { miscRegFile[misc_reg] = val; return NoFault; }
 
 #if FULL_SYSTEM
-        void clearIprs() { };
+        void clearIprs() { }
 
       protected:
         InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
@@ -249,7 +288,7 @@ namespace MipsISA
 
         EPC = 105,//105-112        //14-0 Program counter at last exception
 
-        PRId = 113//113-120,       //15-0 Processor identification and revision
+        PRId = 113,//113-120,       //15-0 Processor identification and revision
         EBase = 114,      //15-1 Exception vector base register
 
         Config = 121,//Bank 16: 121-128
@@ -411,7 +450,7 @@ extern const Addr PageOffset;
         void coldReset();
     };
 
-    StaticInstPtr decodeInst(MachInst);
+    StaticInstPtr decodeInst(ExtMachInst);
 
     // return a no-op instruction... used for instruction fetch faults
     extern const MachInst NoopMachInst;
@@ -422,8 +461,20 @@ extern const Addr PageOffset;
         ITOUCH_ANNOTE = 0xffffffff,
     };
 
-   void getMiscRegIdx(int reg_name,int &idx, int &sel);
+//void getMiscRegIdx(int reg_name,int &idx, int &sel);
 
+    static inline ExtMachInst
+    makeExtMI(MachInst inst, const uint64_t &pc) {
+#if FULL_SYSTEM
+        ExtMachInst ext_inst = inst;
+        if (pc && 0x1)
+            return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
+        else
+            return ext_inst;
+#else
+        return ExtMachInst(inst);
+#endif
+    }
 
     static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
         panic("register classification not implemented");
@@ -470,6 +521,22 @@ extern const Addr PageOffset;
         return 0;
     }
 
+    static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
+    {
+        // check for error condition.  SPARC syscall convention is to
+        // indicate success/failure in reg the carry bit of the ccr
+        // and put the return value itself in the standard return value reg ().
+        if (return_value.successful()) {
+            // no error
+            //regs->miscRegFile.ccrFields.iccFields.c = 0;
+            regs->intRegFile[ReturnValueReg] = return_value.value();
+        } else {
+            // got an error, return details
+            //regs->miscRegFile.ccrFields.iccFields.c = 1;
+            regs->intRegFile[ReturnValueReg] = -return_value.value();
+        }
+    }
+
     // Machine operations
 
     void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
@@ -498,43 +565,6 @@ extern const Addr PageOffset;
     const Addr MaxAddr = (Addr)-1;
 };
 
-#if !FULL_SYSTEM
-class SyscallReturn {
-        public:
-           template <class T>
-           SyscallReturn(T v, bool s)
-           {
-               retval = (uint64_t)v;
-               success = s;
-           }
-
-           template <class T>
-           SyscallReturn(T v)
-           {
-               success = (v >= 0);
-               retval = (uint64_t)v;
-           }
-
-           ~SyscallReturn() {}
-
-           SyscallReturn& operator=(const SyscallReturn& s) {
-               retval = s.retval;
-               success = s.success;
-               return *this;
-           }
-
-           bool successful() { return success; }
-           uint64_t value() { return retval; }
-
-
-       private:
-           uint64_t retval;
-           bool success;
-};
-
-#endif
-
-
 #if FULL_SYSTEM
 //typedef TheISA::InternalProcReg InternalProcReg;
 //const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
@@ -543,4 +573,6 @@ class SyscallReturn {
 #include "arch/mips/mips34k.hh"
 #endif
 
+using namespace MipsISA;
+
 #endif // __ARCH_MIPS_ISA_TRAITS_HH__