FP programs are back to running... Condition Codes can be read and set...

Special Regs (Hi,Lo,FCSR) are now added to the operands for use in decoder.isa.

Now it's back to just debugging execution of code for the release (those unaligned
memory access instruction pairs are still quite the pain i might add)

arch/mips/isa_traits.hh:
    declare functions for .cc file
arch/mips/isa_traits.cc:
    delete unnecessary overloaded functions

    implement condition code functions

    implement round function
arch/mips/isa/base.isa:
    remove R31 constant... define in the operands.isa file instead
arch/mips/isa/decoder.isa:
    wholesale changes once again to FP.

    Now the FP Condition Codes are implemented and the FP programs can
    run and complete to finish.

    Use isnan() instead of my unorderedFP() function

    Also, we now access special regs such as HI,LO,FCSR,etc. just like we do any other reg. operand
arch/mips/isa/operands.isa:
    add more operands for special control regs in int and FP regfiles
arch/mips/isa/formats/branch.isa:
    use R31 instead of r31
arch/mips/isa/formats/fp.isa:
    use MakeCCVector to set Condition Codes in FCSR
arch/mips/regfile/float_regfile.hh:
    treat control regs like any other reg. Just Index them after the regular architectural registers
arch/mips/regfile/int_regfile.hh:
    treat hi,lo as regular int. regs w/special indexing
arch/mips/regfile/regfile.hh:
    no longer need for special register accesses with their own function.

--HG--
rename : arch/mips/regfile.hh => arch/mips/regfile/regfile.hh
extra : convert_revision : 5d2f8fdb59606de2b2e9db3e0a085240561e479e

3 files changed, 230 insertions, 76 deletions

diff --git a/arch/mips/regfile/float_regfile.hh b/arch/mips/regfile/float_regfile.hh
index 308d418a0..15c6f97f4 100644
--- a/arch/mips/regfile/float_regfile.hh
+++ b/arch/mips/regfile/float_regfile.hh
@@ -47,14 +47,6 @@ namespace MipsISA
     {
       protected:
         FloatReg32 regs[NumFloatRegs];
-        FloatReg32 fir;
-        FloatReg32 fcsr;
-
-        FloatReg32 fpcr;
-
-        FloatReg32 fccr;
-        FloatReg32 fexr;
-        FloatReg32 fenr;
 
       public:
 
@@ -65,8 +57,6 @@ namespace MipsISA
 
         double readReg(int floatReg, int width)
         {
-            using namespace std;
-
             switch(width)
             {
               case SingleWidth:
@@ -85,16 +75,23 @@ namespace MipsISA
 
         FloatRegBits readRegBits(int floatReg, int width)
         {
-            switch(width)
-            {
-              case SingleWidth:
-                return regs[floatReg];
-
-              case DoubleWidth:
-                return (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
+            if (floatReg < NumFloatArchRegs - 1) {
+                switch(width)
+                {
+                  case SingleWidth:
+                    return regs[floatReg];
+
+                  case DoubleWidth:
+                    return (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
+
+                  default:
+                    panic("Attempted to read a %d bit floating point register!", width);
+                }
+            } else {
+                if (width > SingleWidth)
+                    assert("Control Regs are only 32 bits wide");
 
-              default:
-                panic("Attempted to read a %d bit floating point register!", width);
+                return regs[floatReg];
             }
         }
 
@@ -144,44 +141,19 @@ namespace MipsISA
             return NoFault;
         }
 
-        MiscReg readFIR()
-        {
-            return fir;
-        }
-
-        Fault setFIR(const MiscReg &val)
-        {
-            fir = val;
-            return NoFault;
-        }
-
-        MiscReg readFCSR()
-        {
-            return fcsr;
-        }
-
-        Fault setFCSR(const MiscReg &val)
-        {
-            fcsr = val;
-            return NoFault;
-        }
-
-        MiscReg readFPCR()
-        {
-            return fpcr;
-        }
-
-        Fault setFPCR(const MiscReg &val)
-        {
-            fpcr = val;
-            return NoFault;
-        }
-
         void serialize(std::ostream &os);
 
         void unserialize(Checkpoint *cp, const std::string &section);
     };
 
+    enum MiscFloatRegNums {
+       FIR = NumFloatArchRegs,
+       FCCR,
+       FEXR,
+       FENR,
+       FCSR
+    };
+
 } // namespace MipsISA
 
 #endif
diff --git a/arch/mips/regfile/int_regfile.hh b/arch/mips/regfile/int_regfile.hh
index cff9eb0d2..3cd87734d 100644
--- a/arch/mips/regfile/int_regfile.hh
+++ b/arch/mips/regfile/int_regfile.hh
@@ -31,6 +31,7 @@
 
 #include "arch/mips/types.hh"
 #include "arch/mips/constants.hh"
+#include "base/misc.hh"
 #include "sim/faults.hh"
 
 class Checkpoint;
@@ -43,8 +44,6 @@ namespace MipsISA
     {
       protected:
         IntReg regs[NumIntRegs];
-        IntReg hi;
-        IntReg lo;
 
       public:
         IntReg readReg(int intReg)
@@ -58,33 +57,17 @@ namespace MipsISA
             return NoFault;
         }
 
-        IntReg readHi()
-        {
-            return hi;
-        }
-
-        Fault setHi(const IntReg &val)
-        {
-            hi = val;
-            return NoFault;
-        }
-
-        IntReg readLo()
-        {
-            return lo;
-        }
-
-        Fault setLo(const IntReg &val)
-        {
-            lo = val;
-            return NoFault;
-        }
-
         void serialize(std::ostream &os);
 
         void unserialize(Checkpoint *cp, const std::string &section);
 
     };
+
+    enum MiscIntRegNums {
+       HI = NumIntArchRegs,
+       LO
+    };
+
 } // namespace MipsISA
 
 #endif
diff --git a/arch/mips/regfile/regfile.hh b/arch/mips/regfile/regfile.hh
new file mode 100644
index 000000000..e77571b33
--- /dev/null
+++ b/arch/mips/regfile/regfile.hh
@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_MIPS_REGFILE_HH__
+#define __ARCH_MIPS_REGFILE_HH__
+
+#include "arch/mips/types.hh"
+#include "arch/mips/constants.hh"
+#include "arch/mips/regfile/int_regfile.hh"
+#include "arch/mips/regfile/float_regfile.hh"
+#include "arch/mips/regfile/misc_regfile.hh"
+#include "sim/faults.hh"
+
+class Checkpoint;
+class ExecContext;
+
+namespace MipsISA
+{
+    class RegFile {
+      protected:
+        IntRegFile intRegFile;		// (signed) integer register file
+        FloatRegFile floatRegFile;	// floating point register file
+        MiscRegFile miscRegFile;	// control register file
+
+      public:
+
+        void clear()
+        {
+            bzero(&intRegFile, sizeof(intRegFile));
+            bzero(&floatRegFile, sizeof(floatRegFile));
+            bzero(&miscRegFile, sizeof(miscRegFile));
+        }
+
+        MiscReg readMiscReg(int miscReg)
+        {
+            return miscRegFile.readReg(miscReg);
+        }
+
+        MiscReg readMiscRegWithEffect(int miscReg,
+                Fault &fault, ExecContext *xc)
+        {
+            fault = NoFault;
+            return miscRegFile.readRegWithEffect(miscReg, fault, xc);
+        }
+
+        Fault setMiscReg(int miscReg, const MiscReg &val)
+        {
+            return miscRegFile.setReg(miscReg, val);
+        }
+
+        Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
+                ExecContext * xc)
+        {
+            return miscRegFile.setRegWithEffect(miscReg, val, xc);
+        }
+
+        FloatReg readFloatReg(int floatReg)
+        {
+            return floatRegFile.readReg(floatReg,SingleWidth);
+        }
+
+        FloatReg readFloatReg(int floatReg, int width)
+        {
+            return floatRegFile.readReg(floatReg,width);
+        }
+
+        FloatRegBits readFloatRegBits(int floatReg)
+        {
+            return floatRegFile.readRegBits(floatReg,SingleWidth);
+        }
+
+        FloatRegBits readFloatRegBits(int floatReg, int width)
+        {
+            return floatRegFile.readRegBits(floatReg,width);
+        }
+
+        Fault setFloatReg(int floatReg, const FloatReg &val)
+        {
+            return floatRegFile.setReg(floatReg, val, SingleWidth);
+        }
+
+        Fault setFloatReg(int floatReg, const FloatReg &val, int width)
+        {
+            return floatRegFile.setReg(floatReg, val, width);
+        }
+
+        Fault setFloatRegBits(int floatReg, const FloatRegBits &val)
+        {
+            return floatRegFile.setRegBits(floatReg, val, SingleWidth);
+        }
+
+        Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
+        {
+            return floatRegFile.setRegBits(floatReg, val, width);
+        }
+
+        IntReg readIntReg(int intReg)
+        {
+            return intRegFile.readReg(intReg);
+        }
+
+        Fault setIntReg(int intReg, const IntReg &val)
+        {
+            return intRegFile.setReg(intReg, val);
+        }
+      protected:
+
+        Addr pc;			// program counter
+        Addr npc;			// next-cycle program counter
+        Addr nnpc;			// next-next-cycle program counter
+                                        // used to implement branch delay slot
+                                        // not real register
+      public:
+        Addr readPC()
+        {
+            return pc;
+        }
+
+        void setPC(Addr val)
+        {
+            pc = val;
+        }
+
+        Addr readNextPC()
+        {
+            return npc;
+        }
+
+        void setNextPC(Addr val)
+        {
+            npc = val;
+        }
+
+        Addr readNextNPC()
+        {
+            return nnpc;
+        }
+
+        void setNextNPC(Addr val)
+        {
+            nnpc = val;
+        }
+
+
+#if FULL_SYSTEM
+        IntReg palregs[NumIntRegs];	// PAL shadow registers
+        InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
+        int intrflag;			// interrupt flag
+        bool pal_shadow;		// using pal_shadow registers
+        inline int instAsid() { return MIPS34K::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
+        inline int dataAsid() { return MIPS34K::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
+#endif // FULL_SYSTEM
+
+        void serialize(std::ostream &os);
+        void unserialize(Checkpoint *cp, const std::string &section);
+
+        typedef int ContextParam;
+        typedef int ContextVal;
+
+        void changeContext(ContextParam param, ContextVal val)
+        {
+        }
+    };
+
+    void copyRegs(ExecContext *src, ExecContext *dest);
+
+    void copyMiscRegs(ExecContext *src, ExecContext *dest);
+
+#if FULL_SYSTEM
+    void copyIprs(ExecContext *src, ExecContext *dest);
+#endif
+} // namespace MipsISA
+
+#endif