name changes ... minor IntOP format change

arch/mips/isa/formats/int.format:
    Looks like Integer Ops with Immediates may not need their own separate class because all those instructions are distinct from
    their reg-reg counterparts

--HG--
rename : arch/mips/isa/bitfields.def => arch/mips/isa/bitfields.isa
rename : arch/mips/isa/decoder.def => arch/mips/isa/decoder.isa
rename : arch/mips/isa/formats.def => arch/mips/isa/formats.isa
rename : arch/mips/isa/includes.h => arch/mips/isa/includes.isa
rename : arch/mips/isa/operands.def => arch/mips/isa/operands.isa
extra : convert_revision : 8e354b4232b28c0264d98d333d55ef8b5a6589cc

7 files changed, 652 insertions, 711 deletions

diff --git a/arch/mips/isa/bitfields.def b/arch/mips/isa/bitfields.isa
index 2b5cd62f1..94a8a6467 100644
--- a/arch/mips/isa/bitfields.def
+++ b/arch/mips/isa/bitfields.isa
@@ -41,11 +41,11 @@ def bitfield SC       < 5: 5>;
 def bitfield OFFSET <15: 0>; // displacement
 
 // Memory-format jumps
-def bitfield JMPTARG	<25: 0>; 
-def bitfield JMPHINT	<10: 6>; 
+def bitfield JMPTARG	<25: 0>;
+def bitfield JMPHINT	<10: 6>;
 
-def bitfield SYSCALLCODE <25: 6>; 
-def bitfield TRAPCODE    <15:13>; 
+def bitfield SYSCALLCODE <25: 6>;
+def bitfield TRAPCODE    <15:13>;
 
 // M5 instructions
 def bitfield M5FUNC <7:0>;
diff --git a/arch/mips/isa/decoder.def b/arch/mips/isa/decoder.def
deleted file mode 100644
index 878c90ca5..000000000
--- a/arch/mips/isa/decoder.def
+++ /dev/null
@@ -1,643 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// The actual MIPS32 ISA decoder 
-// -----------------------------
-// The following instructions are specified in the MIPS32 ISA
-// Specification. Decoding closely follows the style specified 
-// in the MIPS32 ISAthe specification document starting with Table
-// A-2 (document available @ www.mips.com)
-//
-//@todo: Distinguish "unknown/future" use insts from "reserved"
-// ones
-decode OPCODE_HI default FailUnimpl::unknown() {
-    
-    // Derived From ... Table A-2 MIPS32 ISA Manual
-    0x0: decode OPCODE_LO default FailUnimpl::reserved(){
-	
-	0x0: decode FUNCTION_HI {
-	    0x0: decode FUNCTION_LO {
-	      0x1: decode MOVCI {
-		format Move {
-		  0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}});
-		  1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}});
-		}  
-	      }
-
-	      format BasicOp {
-
-		//Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields 
-		//are used to distinguish among the SLL, NOP, SSNOP and EHB functions."
-
-		0x0: sll({{ Rd = Rt.uw << SA; }});
-		
-		0x2: decode SRL {
-		   0: srl({{ Rd = Rt.uw >> SA; }});
-
-		   //Hardcoded assuming 32-bit ISA, probably need parameter here
-		   1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
-		 }	
-	
-		 0x3: sra({{ Rd = Rt.sw >> SA; }});
-		
-		 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
-
-		 0x6: decode SRLV {
-		   0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});
-
-		   //Hardcoded assuming 32-bit ISA, probably need parameter here
-		   1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
-		 }
-
-		 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }});
-	      }
-	    }
-
-	    0x1: decode FUNCTION_LO {
-	     
-	      //Table A-3 Note: "Specific encodings of the hint field are used 
-	      //to distinguish JR from JR.HB and JALR from JALR.HB"
-	      format Jump {
-		0x0: jr(IsReturn);
-		0x1: jalr(IsCall,IsReturn);
-	      }
-
-	      format Move {
-		0x2: movz({{ if (Rt == 0) Rd = Rs; }});
-		0x3: movn({{ if (Rt != 0) Rd = Rs; }});
-	      }
-
-	      format Trap {
-	      	0x4: syscall({{ xc->syscall()}},IsNonSpeculative);
-	      	0x5: break({{ }});
-	      	0x7: sync({{ }});
-	      }
-	    }
-
-	    0x2: decode FUNCTION_LO {
-	      format BasicOp {
-		0x0: mfhi({{ Rd = xc->miscRegs.Hi; }});
-		0x1: mthi({{ xc->miscRegs.Hi = Rs; }});
-		0x2: mflo({{ Rd = xc->miscRegs.Lo; }});
-		0x3: mtlo({{ xc->miscRegs.Lo = Rs; }});
-	      }
-	    };
-
-	    0x3: decode FUNCTION_LO {
-	      format IntOp {
-		0x0: mult({{ 
-			INT64 temp1 = Rs.sw * Rt.sw;
-			xc->miscRegs.Hi->temp1<63:32>;
-			xc->miscRegs.Lo->temp1<31:0>
-		}});
-
-		0x1: multu({{ 
-			INT64 temp1 = Rs.uw * Rt.uw;
-			xc->miscRegs.Hi->temp1<63:32>;
-			xc->miscRegs.Lo->temp1<31:0>
-			Rd.sw = Rs.uw * Rt.uw;
-		}});
-
-		0x2: div({{ 
-			xc->miscRegs.Hi = Rs.sw % Rt.sw;
-			xc->miscRegs.Lo = Rs.sw / Rt.sw;
-			}});	
-
-		0x3: divu({{ 
-			xc->miscRegs.Hi = Rs.uw % Rt.uw;
-			xc->miscRegs.Lo = Rs.uw / Rt.uw;	
-			}});
-	      }
-	    };
-
-	    0x4: decode FUNCTION_LO {
-	      format IntOp {
-		0x0: add({{  Rd.sw = Rs.sw + Rt.sw;}});
-		0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}});
-		0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}});
-		0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}});	      
-		0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}});
-		0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}});
-		0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}});
-		0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}});
-	      }
-	    }
-
-	    0x5: decode FUNCTION_LO {
-	      format IntOp{
-		0x2: slt({{  Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
-		0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
-	      }
-	    };
-
-	    0x6: decode FUNCTION_LO {
-	      format Trap {
-		 0x0: tge({{ }});
-		 0x1: tgeu({{ }});
-		 0x2: tlt({{ }});
-		 0x3: tltu({{ }});
-		 0x4: teq({{ }});
-		 0x6: tne({{ }});
-	      }
-	    }
-	}
-
-	0x1: decode REGIMM_HI {
-	    0x0: decode REGIMM_LO {
-	      format Branch {
-		0x0: bltz({{ cond = (Rs.sq < 0); }});
-		0x1: bgez({{ cond = (Rs.sq >= 0); }});
-
-		//MIPS obsolete instructions
-		0x2: bltzl({{ cond = (Rs.sq < 0); }});
-		0x3: bgezl({{ cond = (Rs.sq >= 0); }});
-	      }
-	    }
-
-	    0x1: decode REGIMM_LO {
-	      format Trap {
-		 0x0: tgei({{ }});
-		 0x1: tgeiu({{ }});
-		 0x2: tlti({{ }});
-		 0x3: tltiu({{ }});
-		 0x4: teqi({{ }});
-		 0x6: tnei({{ }});
-	      }
-	    }
-
-	    0x2: decode REGIMM_LO {
-	      format Branch {
-		0x0: bltzal({{ cond = (Rs.sq < 0); }});
-		0x1: bgezal({{ cond = (Rs.sq >= 0); }});
-
-		//MIPS obsolete instructions
-		0x2: bltzall({{ cond = (Rs.sq < 0); }});
-		0x3: bgezall({{ cond = (Rs.sq >= 0); }});
-	      }
-	    }
-
-	    0x3: decode REGIMM_LO {
-	      format Trap {
-	      	0x7: synci({{ }});
-	      }
-	    }      
-	}
-
-	format Jump {
-	    0x2: j();
-	    0x3: jal(IsCall);
-	}
-
-	format Branch {
-	    0x4: beq({{ cond = (Rs.sq == 0); }});
-	    0x5: bne({{ cond = (Rs.sq !=  0); }});
-	    0x6: blez({{ cond = (Rs.sq <= 0); }});
-	    0x7: bgtz({{ cond = (Rs.sq > 0); }});
-	}
-    };
-
-    0x1: decode OPCODE_LO default FailUnimpl::reserved(){
-	format IntOp {
-	    0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }});
-	    0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}});
-	    0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }});
-	    0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }});
-	    0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}});
-	    0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}});
-	    0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}});
-	    0x7: lui({{ Rt = INTIMM << 16}});
-	};
-    };
-
-    0x2: decode OPCODE_LO default FailUnimpl::reserved(){
-
-      //Table A-11 MIPS32 COP0 Encoding of rs Field
-      0x0: decode RS_MSB {
-	0x0: decode RS {
-	  0x0: mfc0({{ }});
-	  0xC: mtc0({{ }});
-	  0xA: rdpgpr({{ }});
-
-  	  0xB: decode SC {
-	    format BasicOp {
-		0x0: di({{ }});
-		0x1: ei({{ }}); 	      
-	    }
-	  }
-
-  	  0xE: wrpgpr({{ }});
-	}
-
-	//Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
-	0x1: decode FUNCTION {
-	  format Trap {
-	        0x01: tlbr({{ }});
-	        0x02: tlbwi({{ }});
-	        0x06: tlbwr({{ }});
-	        0x08: tlbp({{ }});
-	  }
-
-	  format BasicOp {
-	        0x18: eret({{ }});
-	        0x1F: deret({{ }});
-	        0x20: wait({{ }});
-          }
-	}
-      }
-
-      //Table A-13 MIPS32 COP1 Encoding of rs Field
-      0x1: decode RS_MSB {
-
-	0x0: decode RS_HI {
-	  0x0: decode RS_LO {
-	    0x0: mfc1({{ }});
-	    0x2: cfc1({{ }});
-	    0x3: mfhc1({{ }});
-	    0x4: mtc1({{ }});
-	    0x6: ctc1({{ }});
-	    0x7: mftc1({{ }});
-	  }
-
-	  0x1: decode ND {
-	    0x0: decode TF {
-	      format Branch {
-	      	0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }});
-	      	0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }});
-	      }
-	    }
-
-	    0x1: decode TF {
-	      format Branch {
-		0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }});
-	      	0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }});
-	      }
-	    }
-	  }
-	}
-
-	0x1: decode RS_HI {
-	  0x2: decode RS_LO {
-
-	    //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
-	    //(( single-word ))
-	    0x0: decode RS_HI {
-	      0x0: decode RS_LO {
-		0x0: add_fmt({{ }});
-		0x1: sub_fmt({{ }});
-		0x2: mul_fmt({{ }});
-		0x3: div_fmt({{ }});
-		0x4: sqrt_fmt({{ }});
-		0x5: abs_fmt({{ }});
-		0x6: mov_fmt({{ }});
-		0x7: neg_fmt({{ }});
-	      }
-
-	      0x1: decode RS_LO {
-		//only legal for 64 bit
-		format mode64 {
-		  0x0: round_l({{ }});
-		  0x1: trunc_l({{ }});
-		  0x2: ceil_l({{ }});
-		  0x3: floor_l({{ }});
-		}
-
-		0x4: round_w({{ }});
-		0x5: trunc_w({{ }});
-		0x6: ceil_w({{ }});
-		0x7: floor_w({{ }});
-	      }
-
-	      0x2: decode RS_LO {
-		0x1: decode MOVCF {
-		  0x0: movf_fmt({{ }});
-		  0x1: movt_fmt({{ }});
-		}
-
-		format Move {
-		  0x2: movz({{ if (Rt == 0) Rd = Rs; }});
-         	  0x3: movn({{ if (Rt != 0) Rd = Rs; }});
-	      	}
-
-		format mode64 {
-		  0x2: recip({{ }});
-		  0x3: rsqrt{{ }});
-		}
-	      }
-
-	      0x4: decode RS_LO {
-		0x1: cvt_d({{ }});
-		0x4: cvt_w({{ }});
-
-		//only legal for 64 bit
-		format mode64 {
-		  0x5: cvt_l({{ }});
-		  0x6: cvt_ps({{ }});
-		}
-	      }
-	    }
-
-	    //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D
-	    0x1: decode RS_HI {
-	      0x0: decode RS_LO {
-		0x0: add_fmt({{ }});
-		0x1: sub_fmt({{ }});
-		0x2: mul_fmt({{ }});
-		0x3: div_fmt({{ }});
-		0x4: sqrt_fmt({{ }});
-		0x5: abs_fmt({{ }});
-		0x6: mov_fmt({{ }});
-		0x7: neg_fmt({{ }});
-	      }
-
-	      0x1: decode RS_LO {
-		//only legal for 64 bit
-		format mode64 {
-		  0x0: round_l({{ }});
-		  0x1: trunc_l({{ }});
-		  0x2: ceil_l({{ }});
-		  0x3: floor_l({{ }});
-		}
-
-		0x4: round_w({{ }});
-		0x5: trunc_w({{ }});
-		0x6: ceil_w({{ }});
-		0x7: floor_w({{ }});
-	      }
-
-	      0x2: decode RS_LO {
-		0x1: decode MOVCF {
-		  0x0: movf_fmt({{ }});
-		  0x1: movt_fmt({{ }});
-		}
-
-		format Move {
-		  0x2: movz({{ if (Rt == 0) Rd = Rs; }});
-         	  0x3: movn({{ if (Rt != 0) Rd = Rs; }});
-	      	}
-
-		format mode64 {
-		  0x5: recip({{ }});
-		  0x6: rsqrt{{ }});
-		}
-	      }
-
-	      0x4: decode RS_LO {
-		0x0: cvt_s({{ }});
-		0x4: cvt_w({{ }});
-
-		//only legal for 64 bit
-		format mode64 {
-		  0x5: cvt_l({{ }});
-		}
-	      }
-	    }
-
-	    //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
-	    0x4: decode FUNCTION {
-	      0x10: cvt_s({{ }});
-	      0x10: cvt_d({{ }});
-	    }
-
-	    //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
-	    //Note: "1. Format type L is legal only if 64-bit floating point operations 
-	    //are enabled."
-	    0x5: decode FUNCTION_HI {
-	      0x10: cvt_s({{ }});
-	      0x11: cvt_d({{ }});
-	    }
-
-	    //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
-	    //Note: "1. Format type PS is legal only if 64-bit floating point operations 
-	    //are enabled. "
-	    0x6: decode RS_HI {
-	      0x0: decode RS_LO {
-		0x0: add_fmt({{ }});
-		0x1: sub_fmt({{ }});
-		0x2: mul_fmt({{ }});
-		0x5: abs_fmt({{ }});
-		0x6: mov_fmt({{ }});
-		0x7: neg_fmt({{ }});
-	      }
-
-	      0x2: decode RS_LO {
-		0x1: decode MOVCF {
-		  0x0: movf_fmt({{ }});
-		  0x1: movt_fmt({{ }});
-		}
-
-	      }
-
-	      0x4: decode RS_LO {
-		0x0: cvt_s_pu({{ }});
-	      }
-
-	      0x5: decode RS_LO {
-		0x0: cvt_s_pl({{ }});
-		0x4: pll_s_pl({{ }});
-		0x5: plu_s_pl({{ }});
-		0x6: pul_s_pl({{ }});
-		0x7: puu_s_pl({{ }});
-	      }
-	    }
-      }
-
-      //Table A-19 MIPS32 COP2 Encoding of rs Field 
-      0x2: decode RS_MSB {
-	0x0: decode RS_HI {
-	  0x0: decode RS_LO {
-	    0x0: mfc2({{ }});
-	    0x2: cfc2({{ }});
-	    0x3: mfhc2({{ }});
-	    0x4: mtc2({{ }});
-	    0x6: ctc2({{ }});
-	    0x7: mftc2({{ }});
-	  }
-
-	  0x1: decode ND {
-	    0x0: decode TF {
-	      format Branch { 
-	        0x0: bc2f({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2);
-	        0x1: bc2t({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
-	      }
-	    }
-
-	    0x1: decode TF {
-	      format Branch {
-	      	0x0: bc2fl({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2}});
-	      	0x1: bc2tl({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
-	      }
-	    }
-	  }
-	}
-      }
-
-      //Table A-20 MIPS64 COP1X Encoding of Function Field 1
-      //Note: "COP1X instructions are legal only if 64-bit floating point 
-      //operations are enabled."
-      0x3: decode FUNCTION_HI {
-	0x0: decode FUNCTION_LO {
-	  0x0: lwxc1({{ }});
-	  0x1: ldxc1({{ }});
-	  0x5: luxc1({{ }});
-	}
-
-	0x1: decode FUNCTION_LO {
-	  0x0: swxc1({{ }});
-	  0x1: sdxc1({{ }});
-	  0x5: suxc1({{ }});
-	  0x7: prefx({{ }});
-	}
-
-	0x3: alnv_ps({{ }});
-
-	0x4: decode FUNCTION_LO {
-	  0x0: madd_s({{ }});
-	  0x1: madd_d({{ }});
-	  0x6: madd_ps({{ }});
-	}
-
-	0x5: decode FUNCTION_LO {
-	  0x0: msub_s({{ }});
-	  0x1: msub_d({{ }});
-	  0x6: msub_ps({{ }});	
-	}
-
-	0x6: decode FUNCTION_LO {
-	  0x0: nmadd_s({{ }});
-	  0x1: nmadd_d({{ }});
-	  0x6: nmadd_ps({{ }});	
-	}
-
-	0x7: decode FUNCTION_LO {
-	  0x0: nmsub_s({{ }});
-	  0x1: nmsub_d({{ }});
-	  0x6: nmsub_ps({{ }});
-	}
-      } 
-
-      //MIPS obsolete instructions 
-      0x4: beql({{ cond = (Rs.sq == 0); }});
-      0x5: bnel({{ cond = (Rs.sq != 0); }});
-      0x6: blezl({{ cond = (Rs.sq <= 0); }});
-      0x7: bgtzl({{ cond = (Rs.sq > 0); }});
-    };
-
-    0x3: decode OPCODE_LO default FailUnimpl::reserved() {
-
-	//Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
-	0x4: decode FUNCTION_HI {
-
-	    0x0: decode FUNCTION_LO {
-		format IntOp {
-		   0x0: madd({{ 
-			INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
-			temp1 = temp1 + (Rs.sw * Rt.sw);
-			xc->miscRegs.Hi->temp1<63:32>;
-			xc->miscRegs.Lo->temp1<31:0>
-			}});
-
-	      	   0x1: maddu({{ 
-			INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
-			temp1 = temp1 + (Rs.uw * Rt.uw);
-			xc->miscRegs.Hi->temp1<63:32>;
-			xc->miscRegs.Lo->temp1<31:0>
-			}});
-
-	      	   0x2: mul({{ 	Rd.sw = Rs.sw * Rt.sw; 	}});
-
-	      	   0x4: msub({{ 
-			INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
-			temp1 = temp1 - (Rs.sw * Rt.sw);
-			xc->miscRegs.Hi->temp1<63:32>;
-			xc->miscRegs.Lo->temp1<31:0>
-			}});
-
-	      	   0x5: msubu({{ 
-			INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
-			temp1 = temp1 - (Rs.uw * Rt.uw);
-			xc->miscRegs.Hi->temp1<63:32>;
-			xc->miscRegs.Lo->temp1<31:0>
-			}});
-		}
-	    }
-
-	    0x4: decode FUNCTION_LO {
-	      0x0: clz({{ }});
-	      0x1: clo({{ }});
-	    }
-
-	    0x7: decode FUNCTION_LO {
-	      0x7: sdbbp({{ }});
-	    }	      
-	}
-
-	//Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture
-	0x7: decode FUNCTION_HI {
-	  
-	  0x0: decode FUNCTION_LO {
-	    0x1: ext({{ }});
-	    0x4: ins({{ }});
-	  }
-
-	  //Table A-10 MIPS32 BSHFL Encoding of sa Field
-	  0x4: decode SA {
-	    0x02: wsbh({{ }});
-	    0x10: seb({{ }});
-	    0x18: seh({{ }});
-	  }
-
-	  0x6: decode FUNCTION_LO {
-	    0x7: rdhwr({{ }});
-	  }
-	}
-    };
-
-    0x4: decode OPCODE_LO default FailUnimpl::reserved() {
-	format Memory {
-	    0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }});
-	    0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }});
-	    0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }}, WordAlign);
-	    0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }});
-	    0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }});
-	    0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }});
-	    0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }}, WordAlign);
-	};
-
-	0x7: FailUnimpl::reserved({{ }});
-    };
-
-    0x5: decode OPCODE_LO default FailUnimpl::reserved() {
-	format Memory {
-	    0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }});
-	    0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }});
-	    0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
-	    0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});
-	    0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
-	};
-
-	format FailUnimpl {
-	    0x4: reserved({{ }});
-	    0x5: reserved({{ }});
-	    0x7: cache({{ }});
-	};
-
-    };
-
-    0x6: decode OPCODE_LO default FailUnimpl::reserved() {
-	format Memory {
-	    0x0: ll({{ }});
-	    0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }});
-	    0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }});
-	};
-    };
-
-    0x7: decode OPCODE_LO default FailUnimpl::reserved() {
-	format Memory {
-	    0x0: sc({{ }});
-	    0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }});
-	    0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }});
-	};
-
-    }
-}
-
-
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
new file mode 100644
index 000000000..f0c3fc562
--- /dev/null
+++ b/arch/mips/isa/decoder.isa
@@ -0,0 +1,643 @@
+////////////////////////////////////////////////////////////////////
+//
+// The actual MIPS32 ISA decoder
+// -----------------------------
+// The following instructions are specified in the MIPS32 ISA
+// Specification. Decoding closely follows the style specified
+// in the MIPS32 ISAthe specification document starting with Table
+// A-2 (document available @ www.mips.com)
+//
+//@todo: Distinguish "unknown/future" use insts from "reserved"
+// ones
+decode OPCODE_HI default FailUnimpl::unknown() {
+
+    // Derived From ... Table A-2 MIPS32 ISA Manual
+    0x0: decode OPCODE_LO default FailUnimpl::reserved(){
+
+        0x0: decode FUNCTION_HI {
+            0x0: decode FUNCTION_LO {
+              0x1: decode MOVCI {
+                format Move {
+                  0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}});
+                  1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}});
+                }
+              }
+
+              format BasicOp {
+
+                //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields
+                //are used to distinguish among the SLL, NOP, SSNOP and EHB functions."
+
+                0x0: sll({{ Rd = Rt.uw << SA; }});
+
+                0x2: decode SRL {
+                   0: srl({{ Rd = Rt.uw >> SA; }});
+
+                   //Hardcoded assuming 32-bit ISA, probably need parameter here
+                   1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
+                 }
+
+                 0x3: sra({{ Rd = Rt.sw >> SA; }});
+
+                 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
+
+                 0x6: decode SRLV {
+                   0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});
+
+                   //Hardcoded assuming 32-bit ISA, probably need parameter here
+                   1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
+                 }
+
+                 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }});
+              }
+            }
+
+            0x1: decode FUNCTION_LO {
+
+              //Table A-3 Note: "Specific encodings of the hint field are used
+              //to distinguish JR from JR.HB and JALR from JALR.HB"
+              format Jump {
+                0x0: jr(IsReturn);
+                0x1: jalr(IsCall,IsReturn);
+              }
+
+              format Move {
+                0x2: movz({{ if (Rt == 0) Rd = Rs; }});
+                0x3: movn({{ if (Rt != 0) Rd = Rs; }});
+              }
+
+              format Trap {
+                0x4: syscall({{ xc->syscall()}},IsNonSpeculative);
+                0x5: break({{ }});
+                0x7: sync({{ }});
+              }
+            }
+
+            0x2: decode FUNCTION_LO {
+              format BasicOp {
+                0x0: mfhi({{ Rd = xc->miscRegs.Hi; }});
+                0x1: mthi({{ xc->miscRegs.Hi = Rs; }});
+                0x2: mflo({{ Rd = xc->miscRegs.Lo; }});
+                0x3: mtlo({{ xc->miscRegs.Lo = Rs; }});
+              }
+            };
+
+            0x3: decode FUNCTION_LO {
+              format IntOp {
+                0x0: mult({{
+                        INT64 temp1 = Rs.sw * Rt.sw;
+                        xc->miscRegs.Hi->temp1<63:32>;
+                        xc->miscRegs.Lo->temp1<31:0>
+                }});
+
+                0x1: multu({{
+                        INT64 temp1 = Rs.uw * Rt.uw;
+                        xc->miscRegs.Hi->temp1<63:32>;
+                        xc->miscRegs.Lo->temp1<31:0>
+                        Rd.sw = Rs.uw * Rt.uw;
+                }});
+
+                0x2: div({{
+                        xc->miscRegs.Hi = Rs.sw % Rt.sw;
+                        xc->miscRegs.Lo = Rs.sw / Rt.sw;
+                        }});
+
+                0x3: divu({{
+                        xc->miscRegs.Hi = Rs.uw % Rt.uw;
+                        xc->miscRegs.Lo = Rs.uw / Rt.uw;
+                        }});
+              }
+            };
+
+            0x4: decode FUNCTION_LO {
+              format IntOp {
+                0x0: add({{  Rd.sw = Rs.sw + Rt.sw;}});
+                0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}});
+                0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}});
+                0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}});
+                0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}});
+                0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}});
+                0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}});
+                0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}});
+              }
+            }
+
+            0x5: decode FUNCTION_LO {
+              format IntOp{
+                0x2: slt({{  Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
+                0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
+              }
+            };
+
+            0x6: decode FUNCTION_LO {
+              format Trap {
+                 0x0: tge({{ }});
+                 0x1: tgeu({{ }});
+                 0x2: tlt({{ }});
+                 0x3: tltu({{ }});
+                 0x4: teq({{ }});
+                 0x6: tne({{ }});
+              }
+            }
+        }
+
+        0x1: decode REGIMM_HI {
+            0x0: decode REGIMM_LO {
+              format Branch {
+                0x0: bltz({{ cond = (Rs.sq < 0); }});
+                0x1: bgez({{ cond = (Rs.sq >= 0); }});
+
+                //MIPS obsolete instructions
+                0x2: bltzl({{ cond = (Rs.sq < 0); }});
+                0x3: bgezl({{ cond = (Rs.sq >= 0); }});
+              }
+            }
+
+            0x1: decode REGIMM_LO {
+              format Trap {
+                 0x0: tgei({{ }});
+                 0x1: tgeiu({{ }});
+                 0x2: tlti({{ }});
+                 0x3: tltiu({{ }});
+                 0x4: teqi({{ }});
+                 0x6: tnei({{ }});
+              }
+            }
+
+            0x2: decode REGIMM_LO {
+              format Branch {
+                0x0: bltzal({{ cond = (Rs.sq < 0); }});
+                0x1: bgezal({{ cond = (Rs.sq >= 0); }});
+
+                //MIPS obsolete instructions
+                0x2: bltzall({{ cond = (Rs.sq < 0); }});
+                0x3: bgezall({{ cond = (Rs.sq >= 0); }});
+              }
+            }
+
+            0x3: decode REGIMM_LO {
+              format Trap {
+                0x7: synci({{ }});
+              }
+            }
+        }
+
+        format Jump {
+            0x2: j();
+            0x3: jal(IsCall);
+        }
+
+        format Branch {
+            0x4: beq({{ cond = (Rs.sq == 0); }});
+            0x5: bne({{ cond = (Rs.sq !=  0); }});
+            0x6: blez({{ cond = (Rs.sq <= 0); }});
+            0x7: bgtz({{ cond = (Rs.sq > 0); }});
+        }
+    };
+
+    0x1: decode OPCODE_LO default FailUnimpl::reserved(){
+        format IntOp {
+            0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }});
+            0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}});
+            0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }});
+            0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }});
+            0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}});
+            0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}});
+            0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}});
+            0x7: lui({{ Rt = INTIMM << 16}});
+        };
+    };
+
+    0x2: decode OPCODE_LO default FailUnimpl::reserved(){
+
+      //Table A-11 MIPS32 COP0 Encoding of rs Field
+      0x0: decode RS_MSB {
+        0x0: decode RS {
+          0x0: mfc0({{ }});
+          0xC: mtc0({{ }});
+          0xA: rdpgpr({{ }});
+
+          0xB: decode SC {
+            format BasicOp {
+                0x0: di({{ }});
+                0x1: ei({{ }});
+            }
+          }
+
+          0xE: wrpgpr({{ }});
+        }
+
+        //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
+        0x1: decode FUNCTION {
+          format Trap {
+                0x01: tlbr({{ }});
+                0x02: tlbwi({{ }});
+                0x06: tlbwr({{ }});
+                0x08: tlbp({{ }});
+          }
+
+          format BasicOp {
+                0x18: eret({{ }});
+                0x1F: deret({{ }});
+                0x20: wait({{ }});
+          }
+        }
+      }
+
+      //Table A-13 MIPS32 COP1 Encoding of rs Field
+      0x1: decode RS_MSB {
+
+        0x0: decode RS_HI {
+          0x0: decode RS_LO {
+            0x0: mfc1({{ }});
+            0x2: cfc1({{ }});
+            0x3: mfhc1({{ }});
+            0x4: mtc1({{ }});
+            0x6: ctc1({{ }});
+            0x7: mftc1({{ }});
+          }
+
+          0x1: decode ND {
+            0x0: decode TF {
+              format Branch {
+                0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }});
+                0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }});
+              }
+            }
+
+            0x1: decode TF {
+              format Branch {
+                0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }});
+                0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }});
+              }
+            }
+          }
+        }
+
+        0x1: decode RS_HI {
+          0x2: decode RS_LO {
+
+            //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
+            //(( single-word ))
+            0x0: decode RS_HI {
+              0x0: decode RS_LO {
+                0x0: add_fmt({{ }});
+                0x1: sub_fmt({{ }});
+                0x2: mul_fmt({{ }});
+                0x3: div_fmt({{ }});
+                0x4: sqrt_fmt({{ }});
+                0x5: abs_fmt({{ }});
+                0x6: mov_fmt({{ }});
+                0x7: neg_fmt({{ }});
+              }
+
+              0x1: decode RS_LO {
+                //only legal for 64 bit
+                format mode64 {
+                  0x0: round_l({{ }});
+                  0x1: trunc_l({{ }});
+                  0x2: ceil_l({{ }});
+                  0x3: floor_l({{ }});
+                }
+
+                0x4: round_w({{ }});
+                0x5: trunc_w({{ }});
+                0x6: ceil_w({{ }});
+                0x7: floor_w({{ }});
+              }
+
+              0x2: decode RS_LO {
+                0x1: decode MOVCF {
+                  0x0: movf_fmt({{ }});
+                  0x1: movt_fmt({{ }});
+                }
+
+                format Move {
+                  0x2: movz({{ if (Rt == 0) Rd = Rs; }});
+                  0x3: movn({{ if (Rt != 0) Rd = Rs; }});
+                }
+
+                format mode64 {
+                  0x2: recip({{ }});
+                  0x3: rsqrt{{ }});
+                }
+              }
+
+              0x4: decode RS_LO {
+                0x1: cvt_d({{ }});
+                0x4: cvt_w({{ }});
+
+                //only legal for 64 bit
+                format mode64 {
+                  0x5: cvt_l({{ }});
+                  0x6: cvt_ps({{ }});
+                }
+              }
+            }
+
+            //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D
+            0x1: decode RS_HI {
+              0x0: decode RS_LO {
+                0x0: add_fmt({{ }});
+                0x1: sub_fmt({{ }});
+                0x2: mul_fmt({{ }});
+                0x3: div_fmt({{ }});
+                0x4: sqrt_fmt({{ }});
+                0x5: abs_fmt({{ }});
+                0x6: mov_fmt({{ }});
+                0x7: neg_fmt({{ }});
+              }
+
+              0x1: decode RS_LO {
+                //only legal for 64 bit
+                format mode64 {
+                  0x0: round_l({{ }});
+                  0x1: trunc_l({{ }});
+                  0x2: ceil_l({{ }});
+                  0x3: floor_l({{ }});
+                }
+
+                0x4: round_w({{ }});
+                0x5: trunc_w({{ }});
+                0x6: ceil_w({{ }});
+                0x7: floor_w({{ }});
+              }
+
+              0x2: decode RS_LO {
+                0x1: decode MOVCF {
+                  0x0: movf_fmt({{ }});
+                  0x1: movt_fmt({{ }});
+                }
+
+                format Move {
+                  0x2: movz({{ if (Rt == 0) Rd = Rs; }});
+                  0x3: movn({{ if (Rt != 0) Rd = Rs; }});
+                }
+
+                format mode64 {
+                  0x5: recip({{ }});
+                  0x6: rsqrt{{ }});
+                }
+              }
+
+              0x4: decode RS_LO {
+                0x0: cvt_s({{ }});
+                0x4: cvt_w({{ }});
+
+                //only legal for 64 bit
+                format mode64 {
+                  0x5: cvt_l({{ }});
+                }
+              }
+            }
+
+            //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
+            0x4: decode FUNCTION {
+              0x10: cvt_s({{ }});
+              0x10: cvt_d({{ }});
+            }
+
+            //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
+            //Note: "1. Format type L is legal only if 64-bit floating point operations
+            //are enabled."
+            0x5: decode FUNCTION_HI {
+              0x10: cvt_s({{ }});
+              0x11: cvt_d({{ }});
+            }
+
+            //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
+            //Note: "1. Format type PS is legal only if 64-bit floating point operations
+            //are enabled. "
+            0x6: decode RS_HI {
+              0x0: decode RS_LO {
+                0x0: add_fmt({{ }});
+                0x1: sub_fmt({{ }});
+                0x2: mul_fmt({{ }});
+                0x5: abs_fmt({{ }});
+                0x6: mov_fmt({{ }});
+                0x7: neg_fmt({{ }});
+              }
+
+              0x2: decode RS_LO {
+                0x1: decode MOVCF {
+                  0x0: movf_fmt({{ }});
+                  0x1: movt_fmt({{ }});
+                }
+
+              }
+
+              0x4: decode RS_LO {
+                0x0: cvt_s_pu({{ }});
+              }
+
+              0x5: decode RS_LO {
+                0x0: cvt_s_pl({{ }});
+                0x4: pll_s_pl({{ }});
+                0x5: plu_s_pl({{ }});
+                0x6: pul_s_pl({{ }});
+                0x7: puu_s_pl({{ }});
+              }
+            }
+      }
+
+      //Table A-19 MIPS32 COP2 Encoding of rs Field
+      0x2: decode RS_MSB {
+        0x0: decode RS_HI {
+          0x0: decode RS_LO {
+            0x0: mfc2({{ }});
+            0x2: cfc2({{ }});
+            0x3: mfhc2({{ }});
+            0x4: mtc2({{ }});
+            0x6: ctc2({{ }});
+            0x7: mftc2({{ }});
+          }
+
+          0x1: decode ND {
+            0x0: decode TF {
+              format Branch {
+                0x0: bc2f({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2);
+                0x1: bc2t({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
+              }
+            }
+
+            0x1: decode TF {
+              format Branch {
+                0x0: bc2fl({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2}});
+                0x1: bc2tl({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
+              }
+            }
+          }
+        }
+      }
+
+      //Table A-20 MIPS64 COP1X Encoding of Function Field 1
+      //Note: "COP1X instructions are legal only if 64-bit floating point
+      //operations are enabled."
+      0x3: decode FUNCTION_HI {
+        0x0: decode FUNCTION_LO {
+          0x0: lwxc1({{ }});
+          0x1: ldxc1({{ }});
+          0x5: luxc1({{ }});
+        }
+
+        0x1: decode FUNCTION_LO {
+          0x0: swxc1({{ }});
+          0x1: sdxc1({{ }});
+          0x5: suxc1({{ }});
+          0x7: prefx({{ }});
+        }
+
+        0x3: alnv_ps({{ }});
+
+        0x4: decode FUNCTION_LO {
+          0x0: madd_s({{ }});
+          0x1: madd_d({{ }});
+          0x6: madd_ps({{ }});
+        }
+
+        0x5: decode FUNCTION_LO {
+          0x0: msub_s({{ }});
+          0x1: msub_d({{ }});
+          0x6: msub_ps({{ }});
+        }
+
+        0x6: decode FUNCTION_LO {
+          0x0: nmadd_s({{ }});
+          0x1: nmadd_d({{ }});
+          0x6: nmadd_ps({{ }});
+        }
+
+        0x7: decode FUNCTION_LO {
+          0x0: nmsub_s({{ }});
+          0x1: nmsub_d({{ }});
+          0x6: nmsub_ps({{ }});
+        }
+      }
+
+      //MIPS obsolete instructions
+      0x4: beql({{ cond = (Rs.sq == 0); }});
+      0x5: bnel({{ cond = (Rs.sq != 0); }});
+      0x6: blezl({{ cond = (Rs.sq <= 0); }});
+      0x7: bgtzl({{ cond = (Rs.sq > 0); }});
+    };
+
+    0x3: decode OPCODE_LO default FailUnimpl::reserved() {
+
+        //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
+        0x4: decode FUNCTION_HI {
+
+            0x0: decode FUNCTION_LO {
+                format IntOp {
+                   0x0: madd({{
+                        INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
+                        temp1 = temp1 + (Rs.sw * Rt.sw);
+                        xc->miscRegs.Hi->temp1<63:32>;
+                        xc->miscRegs.Lo->temp1<31:0>
+                        }});
+
+                   0x1: maddu({{
+                        INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
+                        temp1 = temp1 + (Rs.uw * Rt.uw);
+                        xc->miscRegs.Hi->temp1<63:32>;
+                        xc->miscRegs.Lo->temp1<31:0>
+                        }});
+
+                   0x2: mul({{ 	Rd.sw = Rs.sw * Rt.sw; 	}});
+
+                   0x4: msub({{
+                        INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
+                        temp1 = temp1 - (Rs.sw * Rt.sw);
+                        xc->miscRegs.Hi->temp1<63:32>;
+                        xc->miscRegs.Lo->temp1<31:0>
+                        }});
+
+                   0x5: msubu({{
+                        INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
+                        temp1 = temp1 - (Rs.uw * Rt.uw);
+                        xc->miscRegs.Hi->temp1<63:32>;
+                        xc->miscRegs.Lo->temp1<31:0>
+                        }});
+                }
+            }
+
+            0x4: decode FUNCTION_LO {
+              0x0: clz({{ }});
+              0x1: clo({{ }});
+            }
+
+            0x7: decode FUNCTION_LO {
+              0x7: sdbbp({{ }});
+            }
+        }
+
+        //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture
+        0x7: decode FUNCTION_HI {
+
+          0x0: decode FUNCTION_LO {
+            0x1: ext({{ }});
+            0x4: ins({{ }});
+          }
+
+          //Table A-10 MIPS32 BSHFL Encoding of sa Field
+          0x4: decode SA {
+            0x02: wsbh({{ }});
+            0x10: seb({{ }});
+            0x18: seh({{ }});
+          }
+
+          0x6: decode FUNCTION_LO {
+            0x7: rdhwr({{ }});
+          }
+        }
+    };
+
+    0x4: decode OPCODE_LO default FailUnimpl::reserved() {
+        format Memory {
+            0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }});
+            0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }});
+            0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }}, WordAlign);
+            0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }});
+            0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }});
+            0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }});
+            0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }}, WordAlign);
+        };
+
+        0x7: FailUnimpl::reserved({{ }});
+    };
+
+    0x5: decode OPCODE_LO default FailUnimpl::reserved() {
+        format Memory {
+            0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }});
+            0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }});
+            0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
+            0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});
+            0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
+        };
+
+        format FailUnimpl {
+            0x4: reserved({{ }});
+            0x5: reserved({{ }});
+            0x7: cache({{ }});
+        };
+
+    };
+
+    0x6: decode OPCODE_LO default FailUnimpl::reserved() {
+        format Memory {
+            0x0: ll({{ }});
+            0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }});
+            0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }});
+        };
+    };
+
+    0x7: decode OPCODE_LO default FailUnimpl::reserved() {
+        format Memory {
+            0x0: sc({{ }});
+            0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }});
+            0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }});
+        };
+
+    }
+}
+
+
diff --git a/arch/mips/isa/formats.def b/arch/mips/isa/formats.isa
index 404314c7a..404314c7a 100644
--- a/arch/mips/isa/formats.def
+++ b/arch/mips/isa/formats.isa
diff --git a/arch/mips/isa/formats/int.format b/arch/mips/isa/formats/int.format
index 9b2d8d38e..edfdddb18 100644
--- a/arch/mips/isa/formats/int.format
+++ b/arch/mips/isa/formats/int.format
@@ -19,20 +19,6 @@ output header {{
                 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
         };
 
-        /**
-         * Derived class for integer immediate operations.
-         */
-        class IntImm : public IntOp
-        {
-                protected:
-
-                /// Constructor
-                IntegerImm(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
-                {
-                }
-
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-        };
 }};
 
 output decoder {{
@@ -41,7 +27,7 @@ output decoder {{
                 return "Disassembly of integer instruction\n";
         }
 
-        std::string IntImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
         {
                 return "Disassembly of integer immediate instruction\n";
         }
@@ -50,16 +36,9 @@ output decoder {{
 def template IntExecute {{
         Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
         {
-                //These are set to constants when the execute method
-                //is generated
-                bool useCc = ;
-                bool checkPriv = ;
-
                 //Attempt to execute the instruction
                 try
                 {
-                        checkPriv;
-
                         %(op_decl)s;
                         %(op_rd)s;
                         %(code)s;
@@ -74,34 +53,15 @@ def template IntExecute {{
 
                 //Write the resulting state to the execution context
                 %(op_wb)s;
-                if(useCc)
-                {
-                        xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63);
-                        xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0);
-                        xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue;
-                        xc->regs.miscRegFile.ccrFields.iccFields.c = icValue;
-                        xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31);
-                        xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0);
-                        xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue;
-                        xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue;
-                }
+
                 return No_Fault;
         }
 }};
 
 // Primary format for integer operate instructions:
-def format IntegerOp(code, *opt_flags) {{
+def format IntOp(code, *opt_flags) {{
         orig_code = code
         cblk = CodeBlock(code)
-        checkPriv = (code.find('checkPriv') != -1)
-        code.replace('checkPriv', '')
-        if checkPriv:
-                code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
-        else:
-                code.replace('checkPriv;', '')
-        for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
-                       ('xvValue', '0'), ('xcValue', '0')):
-                code.replace(marker, value)
         iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
@@ -109,22 +69,3 @@ def format IntegerOp(code, *opt_flags) {{
         exec_output = IntegerExecute.subst(iop)
 }};
 
-// Primary format for integer operate instructions:
-def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        checkPriv = (code.find('checkPriv') != -1)
-        code.replace('checkPriv', '')
-        if checkPriv:
-                code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
-        else:
-                code.replace('checkPriv;', '')
-        for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
-                       ('xvValue', xvValue), ('xcValue', xcValue)):
-                code.replace(marker, value)
-        iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = IntegerExecute.subst(iop)
-}};
diff --git a/arch/mips/isa/includes.h b/arch/mips/isa/includes.isa
index ff7cb7d1d..ff7cb7d1d 100644
--- a/arch/mips/isa/includes.h
+++ b/arch/mips/isa/includes.isa
diff --git a/arch/mips/isa/operands.def b/arch/mips/isa/operands.isa
index 16d8fbceb..58fa2d3cf 100644
--- a/arch/mips/isa/operands.def
+++ b/arch/mips/isa/operands.isa
@@ -17,8 +17,8 @@ def operands {{
     'Rs': IntRegOperandTraits('uw', 'RS', 'IsInteger', 2),
     'Rt': IntRegOperandTraits('uw', 'RT', 'IsInteger', 3),
 
-    'IntImm': IntRegOperandTraits('uw', 'INTIMM', 'IsInteger', 3),    
-    'Sa': IntRegOperandTraits('uw', 'SA', 'IsInteger', 4),    
+    'IntImm': IntRegOperandTraits('uw', 'INTIMM', 'IsInteger', 3),
+    'Sa': IntRegOperandTraits('uw', 'SA', 'IsInteger', 4),
 
     'Fd': FloatRegOperandTraits('sf', 'FD', 'IsFloating', 1),
     'Fs': FloatRegOperandTraits('sf', 'FS', 'IsFloating', 2),