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authorGabe Black <gblack@eecs.umich.edu>2006-02-12 11:38:26 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-02-12 11:38:26 -0500
commit94590a4dba6712ae61bfed260d7933b58b78c449 (patch)
treecbde4c0a95ab6e064649ec9ffd474a43fdd9b24e /arch/mips
parentb0700182662df6050c5baf46ea6bae2835b55a78 (diff)
parent79613686f0f6a8725e88e935a7c9ff4ede4cfc2b (diff)
downloadgem5-94590a4dba6712ae61bfed260d7933b58b78c449.tar.xz
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch --HG-- extra : convert_revision : 427b5c957f91e66271444acebc01e1a861790363
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/isa/operands.isa29
1 files changed, 14 insertions, 15 deletions
diff --git a/arch/mips/isa/operands.isa b/arch/mips/isa/operands.isa
index 58fa2d3cf..c8e08a436 100644
--- a/arch/mips/isa/operands.isa
+++ b/arch/mips/isa/operands.isa
@@ -13,24 +13,23 @@ def operand_types {{
}};
def operands {{
- 'Rd': IntRegOperandTraits('uw', 'RD', 'IsInteger', 1),
- 'Rs': IntRegOperandTraits('uw', 'RS', 'IsInteger', 2),
- 'Rt': IntRegOperandTraits('uw', 'RT', 'IsInteger', 3),
+ 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
+ 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
+ 'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
- 'IntImm': IntRegOperandTraits('uw', 'INTIMM', 'IsInteger', 3),
- 'Sa': IntRegOperandTraits('uw', 'SA', 'IsInteger', 4),
+ 'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
+ 'Sa': ('IntReg', 'uw', 'SA', 'IsInteger', 4),
- 'Fd': FloatRegOperandTraits('sf', 'FD', 'IsFloating', 1),
- 'Fs': FloatRegOperandTraits('sf', 'FS', 'IsFloating', 2),
- 'Ft': FloatRegOperandTraits('sf', 'FT', 'IsFloating', 3),
+ 'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
+ 'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
+ 'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
- 'Mem': MemOperandTraits('udw', None,
- ('IsMemRef', 'IsLoad', 'IsStore'), 4)
+ 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4)
- #'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
- #'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
- #'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1),
+ #'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
+ #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
+ #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
# The next two are hacks for non-full-system call-pal emulation
- #'R0': IntRegOperandTraits('uq', '0', None, 1),
- #'R16': IntRegOperandTraits('uq', '16', None, 1)
+ #'R0': ('IntReg', 'uq', '0', None, 1),
+ #'R16': ('IntReg', 'uq', '16', None, 1)
}};