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author | Gabe Black <gblack@eecs.umich.edu> | 2006-03-09 18:35:28 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-03-09 18:35:28 -0500 |
commit | 872bbdfc33cb82bf32576db3a57d3055a04acbac (patch) | |
tree | 837dd214bd682ac7efa515b18857bec7d4d35bef /arch/sparc/isa/base.isa | |
parent | 3adb45144aca819c9796168ecde7a263169d9d4d (diff) | |
parent | 7b283dbc090d1197593b00fd1279b92f7c2e693e (diff) | |
download | gem5-872bbdfc33cb82bf32576db3a57d3055a04acbac.tar.xz |
Hand merge. Stuff probably doesn't compile.
--HG--
rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux/process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux/process.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64/process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64/process.hh
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : 7d1efcedd708815d985a951f6f010fbd83dc27e8
Diffstat (limited to 'arch/sparc/isa/base.isa')
-rw-r--r-- | arch/sparc/isa/base.isa | 129 |
1 files changed, 129 insertions, 0 deletions
diff --git a/arch/sparc/isa/base.isa b/arch/sparc/isa/base.isa new file mode 100644 index 000000000..992504369 --- /dev/null +++ b/arch/sparc/isa/base.isa @@ -0,0 +1,129 @@ +//////////////////////////////////////////////////////////////////// +// +// Base class for sparc instructions, and some support functions +// + +output header {{ + + struct condCodes + { + uint8_t c:1; + uint8_t v:1; + uint8_t z:1; + uint8_t n:1; + } + + enum condTest + { + Always=0x8, + Never=0x0, + NotEqual=0x9, + Equal=0x1, + Greater=0xA, + LessOrEqual=0x2, + GreaterOrEqual=0xB, + Less=0x3, + GreaterUnsigned=0xC, + LessOrEqualUnsigned=0x4, + CarryClear=0xD, + CarrySet=0x5, + Positive=0xE, + Negative=0x6, + OverflowClear=0xF, + OverflowSet=0x7 + } + + /** + * Base class for all SPARC static instructions. + */ + class SparcStaticInst : public StaticInst + { + protected: + // Constructor. + SparcStaticInst(const char *mnem, + MachInst _machInst, OpClass __opClass) + : StaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const; + }; + + bool passesCondition(condCodes codes, condTest condition); +}}; + +output decoder {{ + + std::string SparcStaticInst::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream ss; + + ccprintf(ss, "%-10s ", mnemonic); + + // just print the first two source regs... if there's + // a third one, it's a read-modify-write dest (Rc), + // e.g. for CMOVxx + if(_numSrcRegs > 0) + { + printReg(ss, _srcRegIdx[0]); + } + if(_numSrcRegs > 1) + { + ss << ","; + printReg(ss, _srcRegIdx[1]); + } + + // just print the first dest... if there's a second one, + // it's generally implicit + if(_numDestRegs > 0) + { + if(_numSrcRegs > 0) + ss << ","; + printReg(ss, _destRegIdx[0]); + } + + return ss.str(); + } + + bool passesCondition(condCodes codes, condTest condition) + { + switch(condition) + { + case Always: + return true; + case Never: + return false; + case NotEqual: + return !codes.z; + case Equal: + return codes.z; + case Greater: + return !(codes.z | (codes.n ^ codes.v)); + case LessOrEqual: + return codes.z | (codes.n ^ codes.v); + case GreaterOrEqual: + return !(codes.n ^ codes.v); + case Less: + return (codes.n ^ codes.v); + case GreaterUnsigned: + return !(codes.c | codes.z); + case LessOrEqualUnsigned: + return (codes.c | codes.z); + case CarryClear: + return !codes.c; + case CarrySet: + return codes.c; + case Positive: + return !codes.n; + case Negative: + return codes.n; + case OverflowClear: + return !codes.v; + case OverflowSet: + return codes.v; + } + } +}}; + |