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author | Ali Saidi <saidi@eecs.umich.edu> | 2006-03-16 23:09:01 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-03-16 23:09:01 -0500 |
commit | cf942425393dbd7ac3d05a9c94aab5140d0bf617 (patch) | |
tree | 782f40e1f4bebed7651b2234d6f26988963db543 /arch/sparc/isa/bitfields.isa | |
parent | fc5d25bdb63bd47e51a47111258d9edf1232a23b (diff) | |
download | gem5-cf942425393dbd7ac3d05a9c94aab5140d0bf617.tar.xz |
clean up condition codes a little bit
put back in Tcc code that was deleted in last merge
arch/sparc/isa/bitfields.isa:
clean up condition codes a little bit
--HG--
extra : convert_revision : c554fd5c3ee8cfd6643f69f8351124a7a4b5d9fa
Diffstat (limited to 'arch/sparc/isa/bitfields.isa')
-rw-r--r-- | arch/sparc/isa/bitfields.isa | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/arch/sparc/isa/bitfields.isa b/arch/sparc/isa/bitfields.isa index 237f0fa64..988f067c6 100644 --- a/arch/sparc/isa/bitfields.isa +++ b/arch/sparc/isa/bitfields.isa @@ -7,13 +7,11 @@ // simply defined alphabetically def bitfield A <29>; -def bitfield CC02 <20>; -def bitfield CC03 <25>; -def bitfield CC04 <11>; -def bitfield CC12 <21>; -def bitfield CC13 <26>; -def bitfield CC14 <12>; -def bitfield CC2 <18>; +def bitfield BPCC <21:20>; // for BPcc & FBPcc +def bitfield FCMPCC <26:56>; // for FCMP & FCMPEa +def bitflied FMOVCC <13:11>; // for FMOVcc +def bitfield CC <12:11>; // for MOVcc & Tcc +def bitfierd MOVCC3 <18>; // also for MOVcc def bitfield CMASK <6:4>; def bitfield COND2 <28:25>; def bitfield COND4 <17:14>; |