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author | Gabe Black <gblack@eecs.umich.edu> | 2006-03-09 18:35:28 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-03-09 18:35:28 -0500 |
commit | 872bbdfc33cb82bf32576db3a57d3055a04acbac (patch) | |
tree | 837dd214bd682ac7efa515b18857bec7d4d35bef /arch/sparc/isa/bitfields.isa | |
parent | 3adb45144aca819c9796168ecde7a263169d9d4d (diff) | |
parent | 7b283dbc090d1197593b00fd1279b92f7c2e693e (diff) | |
download | gem5-872bbdfc33cb82bf32576db3a57d3055a04acbac.tar.xz |
Hand merge. Stuff probably doesn't compile.
--HG--
rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux/process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux/process.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64/process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64/process.hh
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : 7d1efcedd708815d985a951f6f010fbd83dc27e8
Diffstat (limited to 'arch/sparc/isa/bitfields.isa')
-rw-r--r-- | arch/sparc/isa/bitfields.isa | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/sparc/isa/bitfields.isa b/arch/sparc/isa/bitfields.isa new file mode 100644 index 000000000..b0ac57575 --- /dev/null +++ b/arch/sparc/isa/bitfields.isa @@ -0,0 +1,50 @@ +//////////////////////////////////////////////////////////////////// +// +// Bitfield definitions. +// + +// Bitfields are shared liberally between instruction formats, so they are +// simply defined alphabetically + +def bitfield A <29>; +def bitfield CC02 <20>; +def bitfield CC03 <25>; +def bitfield CC04 <11>; +def bitfield CC12 <21>; +def bitfield CC13 <26>; +def bitfield CC14 <12>; +def bitfield CC2 <18>; +def bitfield CMASK <6:4>; +def bitfield COND2 <28:25>; +def bitfield COND4 <17:14>; +def bitfield D16HI <21:20>; +def bitfield D16LO <13:0>; +def bitfield DISP19 <18:0>; +def bitfield DISP22 <21:0>; +def bitfield DISP30 <29:0>; +def bitfield FCN <29:26>; +def bitfield I <13>; +def bitfield IMM_ASI <12:5>; +def bitfield IMM22 <21:0>; +def bitfield MMASK <3:0>; +def bitfield OP <31:30>; +def bitfield OP2 <24:22>; +def bitfield OP3 <24:19>; +def bitfield OPF <13:5>; +def bitfield OPF_CC <13:11>; +def bitfield OPF_LOW5 <9:5>; +def bitfield OPF_LOW6 <10:5>; +def bitfield P <19>; +def bitfield RCOND2 <27:25>; +def bitfield RCOND3 <12:10>; +def bitfield RCOND4 <12:10>; +def bitfield RD <29:25>; +def bitfield RS1 <18:14>; +def bitfield RS2 <4:0>; +def bitfield SHCNT32 <4:0>; +def bitfield SHCNT64 <5:0>; +def bitfield SIMM10 <9:0>; +def bitfield SIMM11 <10:0>; +def bitfield SIMM13 <12:0>; +def bitfield SW_TRAP <6:0>; +def bitfield X <12>; |