summaryrefslogtreecommitdiff
path: root/arch/sparc/isa/bitfields.isa
diff options
context:
space:
mode:
authorAli Saidi <saidi@eecs.umich.edu>2006-03-15 18:12:01 -0500
committerAli Saidi <saidi@eecs.umich.edu>2006-03-15 18:12:01 -0500
commit7359e2df01fde9ea34a0ba661750a455e26bcacd (patch)
treef584d8fce74b08639346b80003f735d53f0e94e0 /arch/sparc/isa/bitfields.isa
parent97e424982ad99348bc27ab2ca79d0861cddfe4d1 (diff)
downloadgem5-7359e2df01fde9ea34a0ba661750a455e26bcacd.tar.xz
implement the Tcc instruction to call syscall.
arch/sparc/isa/bitfields.isa: the trap field is 7:0 arch/sparc/isa/decoder.isa: add code to in the Tcc instruction to call a syscall arch/sparc/isa_traits.hh: We need the syscall num register --HG-- extra : convert_revision : 0861ec1dd8c7cac57765b22bc408fdffbe63fe2a
Diffstat (limited to 'arch/sparc/isa/bitfields.isa')
-rw-r--r--arch/sparc/isa/bitfields.isa2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/sparc/isa/bitfields.isa b/arch/sparc/isa/bitfields.isa
index b0ac57575..237f0fa64 100644
--- a/arch/sparc/isa/bitfields.isa
+++ b/arch/sparc/isa/bitfields.isa
@@ -46,5 +46,5 @@ def bitfield SHCNT64 <5:0>;
def bitfield SIMM10 <9:0>;
def bitfield SIMM11 <10:0>;
def bitfield SIMM13 <12:0>;
-def bitfield SW_TRAP <6:0>;
+def bitfield SW_TRAP <7:0>;
def bitfield X <12>;